 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| v850es/kf1+ 32-bit single-chip microcontrollers hardware printed in japan document no. u16895ej1v0ud00 (1st edition) date published june 2004 n cp(k) preliminary user?s manual pd703308 pd703308y pd70f3306 pd70f3306y pd70f3308 pd70f3308y 2004
preliminary user?s manual u16895ej1v0ud 2 [memo] preliminary user?s manual u16895ej1v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. caution: pd70f3306, 70f3306y, 70f3308, and 70f3308y use superflash ? technology licensed from silicon storage technology, inc. windows and windows nt are either re gistered trademarks or trademar ks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. preliminary user?s manual u16895ej1v0ud 4 solaris and sunos are trademar ks of sun microsystems, inc. superflash is a registered trademark of s ilicon storage technology, inc. in several countries including the united states and japan. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics products depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. ? ? ? ? ? ? ? m5d 02. 11-1 the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": preliminary user?s manual u16895ej1v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: preliminary user?s manual u16895ej1v0ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/kf1+ and design applicat ion systems using these products. purpose this manual is intended to give users an under standing of the hardw are functions of the v850es/kf1+ shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? cpu function ? on-chip peripheral functions ? flash memory programming ? electrical specifications (target) ? data types ? register set ? instruction format and instruction set ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to find the details of a register where the name is known refer to appendix c register index . to understand the details of an instruction function refer to the v850es architecture user?s manual . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the overall func tions of the v850es/kf1+ read this manual according to the contents . to know the electrical specif ications of the v850es/kf1+ refer to chapter 30 electrical specifications (target) . the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx.yyy? is de scribed as is in a program, however, the compiler/assembler cannot recognize it correctly. preliminary user?s manual u16895ej1v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 preliminary user?s manual u16895ej1v0ud 8 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/kf1+ document name document no. v850es architecture user?s manual u15943e v850es/kx1, v850es/kx1+ on-chip debug user?s manual u16972e v850es/kf1+ hardware user?s manual this manual documents related to developm ent tools (user?s manuals) document name document no. operation u16053e c language u16054e ca850 ver. 2.50 c compiler package assembly language u16042e pm plus ver. 5.10 u16569e id850qb ver. 2.80 integrated debugger operation u16973e operation u16906e sm plus ver. 1.00 system simulator user open interface specifications u16907e basics u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e basics u13773e installation u13774e rx850 pro ver. 3.15 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.20 system performance analyzer u14410e pg-fp4 flash memory programmer u15260e preliminary user?s manual u16895ej1v0ud 9 contents chapter 1 introduction ...................................................................................................... ...........18 1.1 k1 family product lineup................................................................................................... ...... 18 1.1.1 v850es/kx1+, v850 es/kx1 products lineup.................................................................................. 18 1.1.2 78k0/kx1+, 78k0/k x1 products lineup ...................................................................................... .....21 1.2 features ................................................................................................................... ................... 24 1.3 applications............................................................................................................... ................. 26 1.4 ordering information ....................................................................................................... .......... 26 1.5 pin configuration (top view).................................... ........................................................... ..... 27 1.6 function block configuration .................................... ........................................................... ... 29 1.7 overview of functions ...................................................................................................... ........ 33 chapter 2 pin functions .................................................................................................... ............34 2.1 list of pin functions ...................................................................................................... ........... 34 2.2 pin status................................................................................................................. ................... 40 2.3 pin i/o circuits and recommende d connection of unused pins......................................... 41 2.4 pin i/o circuits ........................................................................................................... ................ 43 chapter 3 cpu functions .................................................................................................... ..........45 3.1 features ................................................................................................................... ................... 45 3.2 cpu register set ........................................................................................................... ............ 46 3.2.1 program re gister set ..................................................................................................... ..................47 3.2.2 system r egister set...................................................................................................... ...................48 3.3 operating modes............................................................................................................ ............ 54 3.4 address space .............................................................................................................. ............. 55 3.4.1 cpu addr ess s pace........................................................................................................ ................55 3.4.2 wraparound of cpu address space .......................................................................................... .....56 3.4.3 memo ry map............................................................................................................... ....................57 3.4.4 areas .................................................................................................................... ..........................59 3.4.5 recommended us e of addres s space ......................................................................................... ...63 3.4.6 peripheral i/o registers................................................................................................. ..................66 3.4.7 special registers ........................................................................................................ .....................74 3.4.8 c autio ns ................................................................................................................. ........................78 chapter 4 port functions ................................................................................................... .........82 4.1 features ................................................................................................................... ................... 82 4.2 basic port configuration................................................................................................... ........ 82 4.3 port configuratio n ......................................................................................................... ............ 83 4.3.1 port 0................................................................................................................... ...........................88 4.3.2 port 3................................................................................................................... ...........................90 4.3.3 port 4................................................................................................................... ...........................95 4.3.4 port 5................................................................................................................... ...........................98 4.3.5 port 7................................................................................................................... .........................101 4.3.6 port 9................................................................................................................... .........................102 4.3.7 po rt cm .................................................................................................................. ......................108 preliminary user?s manual u16895ej1v0ud 10 4.3.8 po rt cs .................................................................................................................. ...................... 110 4.3.9 po rt ct .................................................................................................................. ...................... 112 4.3.10 po rt dl................................................................................................................. ........................ 114 4.4 block diagrams ............................................................................................................. ........... 117 4.5 port register setting when al ternate function is used...................................................... 140 4.6 cautions ................................................................................................................... ................. 146 4.6.1 cautions on bit manipulation inst ruction for port n register (pn) .................................................. 146 4.6.2 hysteresis characteri stics ............................................................................................... ............. 147 chapter 5 bus control function .......................................................................................... 14 8 5.1 features ................................................................................................................... ................. 148 5.2 bus control pins ........................................................................................................... ........... 149 5.2.1 pin status when internal rom, internal ram, or on-chip peri pheral i/o is accesse d................... 149 5.2.2 pin status in each operat ion m ode........................................................................................ ....... 149 5.3 memory block function ...................................................................................................... .... 150 5.3.1 chip select control f unction............................................................................................. ............. 151 5.4 bus access ................................................................................................................. .............. 152 5.4.1 number of clocks for access.............................................................................................. .......... 152 5.4.2 bus size se tting f unction ................................................................................................ .............. 152 5.4.3 access by bus size ....................................................................................................... ............... 153 5.5 wait function.............................................................................................................. .............. 160 5.5.1 programmable wait f unction ............................................................................................... ......... 160 5.5.2 external wait function................................................................................................... ................ 161 5.5.3 relationship betw een programmable wait and external wait ....................................................... 161 5.5.4 programmable addr ess wait function....................................................................................... .... 162 5.6 idle state inserti on function.............................................................................................. ..... 163 5.7 bus hold function .......................................................................................................... ......... 164 5.7.1 function al out line....................................................................................................... .................. 164 5.7.2 bus hold proce dure....................................................................................................... ............... 165 5.7.3 operation in power save mode ............................................................................................. ....... 165 5.8 bus priority ............................................................................................................... ................ 166 5.9 bus timing................................................................................................................. ............... 167 5.10 cautions .................................................................................................................. .................. 170 chapter 6 clock generation function............................................................................... 171 6.1 overview ................................................................................................................... ................ 171 6.2 configuration.............................................................................................................. .............. 172 6.3 registers .................................................................................................................. ................. 174 6.4 operation .................................................................................................................. ................ 179 6.4.1 operation of each clock .................................................................................................. ............. 179 6.4.2 clock output function .................................................................................................... ............... 179 6.4.3 external clo ck input f unction ............................................................................................ ............ 179 6.5 pll function ............................................................................................................... ............. 180 6.5.1 ov ervi ew................................................................................................................. ..................... 180 6.5.2 r egist er ................................................................................................................. ...................... 180 6.5.3 usage .................................................................................................................... ...................... 181 chapter 7 16-bit timer/event counter p (tmp)................................................................. 182 preliminary user?s manual u16895ej1v0ud 11 7.1 overview ....................................................................................................................... ............ 182 7.2 functions ...................................................................................................................... ............ 182 7.3 configuration.................................................................................................................. .......... 183 7.4 registers...................................................................................................................... ............. 185 7.5 operation ...................................................................................................................... ............ 196 7.5.1 interval timer mode (tp0md2 to tp0md0 bi ts = 000).................................................................. 197 7.5.2 external event count mode (tp0 md2 to tp0md0 bits = 001) ......................................................207 7.5.3 external trigger pulse output mode (tp0md2 to tp0md0 bits = 010) ..........................................215 7.5.4 one-shot pulse output mode (tp0md 2 to tp0md0 bi ts = 01 1) ................................................... 227 7.5.5 pwm output mode (tp0md2 to tp0md0 bi ts = 100) ...................................................................234 7.5.6 free-running timer mode (tp0md 2 to tp0md0 bits = 101) ......................................................... 243 7.5.7 pulse width measurement mode (tp0 md2 to tp0md0 bits = 110) ............................................. 260 7.5.8 timer output operat ions........................................................................................................ ........266 7.6 eliminating noise on capture trigger input pin (tip 0a)...................................................... 267 7.7 cautions....................................................................................................................... ............. 269 chapter 8 16-bit timer/event counter 0..............................................................................270 8.1 functions .................................................................................................................. ................ 270 8.2 configuration.............................................................................................................. .............. 270 8.3 registers.................................................................................................................. ................. 275 8.4 operation .................................................................................................................. ................ 283 8.4.1 operation as interval timer .............................................................................................. .............283 8.4.2 ppg output operation ..................................................................................................... ..............286 8.4.3 pulse widt h measur ement .................................................................................................. ..........290 8.4.4 operation as ex ternal event count er...................................................................................... .......301 8.4.5 square-wave output oper ation............................................................................................. .........304 8.4.6 one-shot puls e output op eration .......................................................................................... ........307 8.4.7 c autio ns ................................................................................................................. ......................313 chapter 9 8-bit timer/event counter 5................................................................................318 9.1 functions .................................................................................................................. ................ 318 9.2 configuration.............................................................................................................. .............. 319 9.3 registers.................................................................................................................. ................. 322 9.4 operation .................................................................................................................. ................ 325 9.4.1 operation as interval timer .............................................................................................. .............325 9.4.2 operation as ex ternal event count er...................................................................................... .......327 9.4.3 square-wave output oper ation............................................................................................. .........328 9.4.4 8-bit pwm output oper ation ............................................................................................... ...........330 9.4.5 operation as inte rval timer (16 bits).................................................................................... ..........333 9.4.6 operation as external event counter (16 bits)............................................................................ ...335 9.4.7 square-wave output oper ation (16-bit resolu tion)......................................................................... 336 9.4.8 c autio ns ................................................................................................................. ......................337 chapter 10 8-bit timer h .................................................................................................. ............338 10.1 functions ................................................................................................................. ................. 338 10.2 configuration............................................................................................................. ............... 338 10.3 registers................................................................................................................. .................. 341 preliminary user?s manual u16895ej1v0ud 12 10.4 operation ................................................................................................................. ................. 345 10.4.1 operation as interval timer/square wave output .......................................................................... . 345 10.4.2 pwm output mode oper ation ............................................................................................... ........ 348 10.4.3 carrier generat or mode o peratio n........................................................................................ ........ 354 chapter 11 interval timer, watch timer ........................................................................... 361 11.1 interval timer brg........................................................................................................ ........... 361 11.1.1 f uncti ons ............................................................................................................... ...................... 361 11.1.2 config uration ........................................................................................................... .................... 361 11.1.3 regi sters............................................................................................................... ....................... 363 11.1.4 oper ation ............................................................................................................... ...................... 365 11.2 watch timer............................................................................................................... ............... 366 11.2.1 f uncti ons ............................................................................................................... ...................... 366 11.2.2 config uration ........................................................................................................... .................... 366 11.2.3 r egist er ................................................................................................................ ....................... 367 11.2.4 oper ation ............................................................................................................... ...................... 369 11.3 cautions .................................................................................................................. .................. 370 chapter 12 watchdog timer functions .............................................................................. 372 12.1 watchdog timer 1 .......................................................................................................... .......... 372 12.1.1 f uncti ons ............................................................................................................... ...................... 372 12.1.2 config uration ........................................................................................................... .................... 374 12.1.3 regi sters............................................................................................................... ....................... 374 12.1.4 oper ation ............................................................................................................... ...................... 376 12.2 watchdog timer 2 .......................................................................................................... .......... 378 12.2.1 f uncti ons ............................................................................................................... ...................... 378 12.2.2 config uration ........................................................................................................... .................... 379 12.2.3 regi sters............................................................................................................... ....................... 379 12.2.4 oper ation ............................................................................................................... ...................... 381 chapter 13 real-time output function (rto) ................................................................... 382 13.1 function .................................................................................................................. .................. 382 13.2 configuration............................................................................................................. ............... 383 13.3 registers ................................................................................................................. .................. 384 13.4 operation ................................................................................................................. ................. 386 13.5 usage..................................................................................................................... .................... 387 13.6 cautions .................................................................................................................. .................. 387 13.7 security function ......................................................................................................... ............ 388 chapter 14 a/d converter ................................................................................................... ...... 390 14.1 overview .................................................................................................................. ................. 390 14.2 functions ................................................................................................................. ................. 390 14.3 configuration............................................................................................................. ............... 391 14.4 registers ................................................................................................................. .................. 393 14.5 operation ................................................................................................................. ................. 401 14.5.1 basic operation ......................................................................................................... ................... 401 14.5.2 trigger modes........................................................................................................... ................... 402 preliminary user?s manual u16895ej1v0ud 13 14.5.3 operat ion mo des ......................................................................................................... .................403 14.5.4 power fail det ection f unction........................................................................................... ..............406 14.5.5 setti ng meth od .......................................................................................................... ...................407 14.6 cautions.................................................................................................................. .................. 408 14.7 how to read a/d converter char acteristics table .............................................................. 414 chapter 15 asynchronous serial interface (uart) .....................................................418 15.1 features .................................................................................................................. .................. 418 15.2 configuration............................................................................................................. ............... 419 15.3 registers................................................................................................................. .................. 421 15.4 interrupt request signals ...... ........................................................................................... ...... 428 15.5 operation ................................................................................................................. ................. 429 15.5.1 data format............................................................................................................. ......................429 15.5.2 transmi t operat ion...................................................................................................... ..................430 15.5.3 continuous trans mission op eration ....................................................................................... .......432 15.5.4 receive operat ion....................................................................................................... ..................436 15.5.5 recept ion error......................................................................................................... ....................437 15.5.6 parity types and corresponding operatio n ................................................................................ ....439 15.5.7 receive dat a noise filter ............................................................................................... ................440 15.5.8 sbf transmission/re ception (uar t0 only) ................................................................................. ..441 15.6 dedicated baud rate generator n (brgn).............. .............................................................. 445 15.6.1 baud rate generator n (brgn) conf igurat ion .............................................................................. ..445 15.6.2 serial cl ock gener ation ................................................................................................. ................446 15.6.3 baud rate setting ex ample ............................................................................................... .............449 15.6.4 allowable baud rate range during reception .............................................................................. ...450 15.6.5 transfer rate during continuous transmi ssion............................................................................ ...452 15.7 cautions.................................................................................................................. .................. 452 chapter 16 clocked serial interface 0 (csi0).................................................................453 16.1 features .................................................................................................................. .................. 453 16.2 configuration............................................................................................................. ............... 454 16.3 registers................................................................................................................. .................. 457 16.4 operation ................................................................................................................. ................. 466 16.4.1 transmission/reception completion in terrupt request si gnal (intcs i0n) ......................................466 16.4.2 single tr ansfer mode .................................................................................................... ................468 16.4.3 continuous transfe r mode ................................................................................................ ............471 16.5 output pins............................................................................................................... ................ 479 chapter 17 clocked serial interface a (csia) with automatic transmit/receive function.................................................................................480 17.1 functions ................................................................................................................. ................. 480 17.2 configuration............................................................................................................. ............... 481 17.3 registers................................................................................................................. .................. 483 17.4 operation ................................................................................................................. ................. 491 17.4.1 3-wire se rial i/o mode .................................................................................................. ................491 17.4.2 3-wire serial i/o mode with auto matic transmit/recei ve func tion ...................................................495 preliminary user?s manual u16895ej1v0ud 14 chapter 18 i 2 c bus ......................................................................................................................... . 511 18.1 features .................................................................................................................. .................. 511 18.2 configuration............................................................................................................. ............... 514 18.3 registers ................................................................................................................. .................. 516 18.4 functions ................................................................................................................. ................. 529 18.4.1 pin conf iguration ....................................................................................................... ................... 529 18.5 i 2 c bus definitions and control methods ......................... ..................................................... 530 18.5.1 start conditi on......................................................................................................... ..................... 530 18.5.2 addr esses............................................................................................................... ..................... 531 18.5.3 transfer direct ion specif ication ........................................................................................ ............ 531 18.5.4 acknowled ge signal (ack) ................................................................................................ .......... 532 18.5.5 stop c onditio n .......................................................................................................... .................... 533 18.5.6 wait si gnal (w ait)...................................................................................................... ................. 534 18.6 i 2 c interrupt request signals (intiic0) .......................... ........................................................ 536 18.6.1 master dev ice operat ion................................................................................................. .............. 536 18.6.2 slave device operation (when receivin g slave address data (matc h with addr ess)) .................... 539 18.6.3 slave device operation (w hen receiving ex tension code) ............................................................ 543 18.6.4 operation with out communi cation......................................................................................... ....... 547 18.6.5 arbitration loss oper ation (operation as slave after arbitrat ion lo ss) ............................................ 547 18.6.6 operation when arbitrat ion loss occurs (no communicati on after arbitr ation lo ss) ....................... 549 18.7 interrupt request signal (intiic 0) generation timing and wait c ontrol........................... 554 18.8 address match detection method .......................................................................................... 55 5 18.9 error detection ........................................................................................................... .............. 555 18.10 extension code ........................................................................................................... ............. 556 18.11 arbitration .............................................................................................................. ................... 557 18.12 wakeup function .......................................................................................................... ........... 558 18.13 communication reservation ................................................................................................ .. 559 18.13.1 when communication reservation functi on is enabled (iicf0 .iicrsv0 bi t = 0) ........................... 559 18.13.2 when communication reservation function is disabled (iicf0 .iicrsv0 bi t = 1) .......................... 562 18.14 cautions ................................................................................................................. ................... 563 18.15 communication operations ................................................................................................. ... 563 18.15.1 master operati on 1..................................................................................................... .................. 563 18.15.2 master operati on 2..................................................................................................... .................. 565 18.15.3 slave operation........................................................................................................ .................... 566 18.16 timing of data communication ............................................................................................. . 569 chapter 19 interrupt/exception processing function............................................... 576 19.1 overview .................................................................................................................. ................. 576 19.1.1 f eatur es................................................................................................................ ....................... 576 19.2 non-maskable interrupts ................................................................................................... ...... 579 19.2.1 oper ation ............................................................................................................... ...................... 582 19.2.2 re store ................................................................................................................. ....................... 583 19.2.3 np flag ................................................................................................................. ........................ 584 19.3 maskable interrupts ....................................................................................................... .......... 585 19.3.1 oper ation ............................................................................................................... ...................... 585 19.3.2 re store ................................................................................................................. ....................... 587 19.3.3 priorities of maskable in terrupts....................................................................................... ............ 588 preliminary user?s manual u16895ej1v0ud 15 19.3.4 interrupt contro l register (xxlcn) ...................................................................................... .............592 19.3.5 interrupt mask registers 0, 1, 3 (imr0, imr1, im r3) ....................................................................5 94 19.3.6 in-service priori ty register (ispr)..................................................................................... .............595 19.3.7 id flag ................................................................................................................. ..........................596 19.3.8 watchdog timer mode register 1 (wdtm1) .................................................................................. 597 19.4 external interrupt requ est input pins (nmi, intp0 to intp7) .... ......................................... 598 19.4.1 noise e liminat ion ....................................................................................................... ...................598 19.4.2 edge de tection.......................................................................................................... ....................600 19.5 software exceptions....................................................................................................... ......... 604 19.5.1 oper ation............................................................................................................... .......................604 19.5.2 re store ................................................................................................................. ........................605 19.5.3 ep flag................................................................................................................. .........................606 19.6 exception trap ............................................................................................................ ............. 607 19.6.1 ill egal opc ode .......................................................................................................... .....................607 19.6.2 debu g tr ap.............................................................................................................. ......................609 19.7 multiple interrupt servicing co ntrol ...................................................................................... 611 19.8 interrupt response time................................................................................................... ...... 613 19.9 periods in which interrupts are not acknowledge d by cpu ............................................. 614 19.10 cautions................................................................................................................. ................... 614 chapter 20 key interrupt function ......................................................................................615 20.1 function .................................................................................................................. .................. 615 20.2 register.................................................................................................................. ................... 616 chapter 21 standby function ................................................................................................ ...617 21.1 overview .................................................................................................................. ................. 617 21.2 registers................................................................................................................. .................. 620 21.3 halt mode ................................................................................................................. .............. 623 21.3.1 setting and op eration status ............................................................................................ .............623 21.3.2 releasin g halt mode ..................................................................................................... ............623 21.4 idle mode................................................................................................................. ................ 625 21.4.1 setting and op eration status ............................................................................................ .............625 21.4.2 releasin g idle mode ..................................................................................................... ..............626 21.5 stop mode ................................................................................................................. .............. 628 21.5.1 setting and op eration status ............................................................................................ .............628 21.5.2 releasin g stop mode ..................................................................................................... ............629 21.5.3 securing oscillation stabilizati on time when stop m ode is rel eased ...........................................631 21.6 subclock operation mode................................................................................................... .... 632 21.6.1 setting and op eration status ............................................................................................ .............632 21.6.2 releasing subc lock operat ion mode....................................................................................... ......632 21.7 sub-idle mode............................................................................................................. ............ 634 21.7.1 setting and op eration status ............................................................................................ .............634 21.7.2 releasing sub-idle mode................................................................................................. ...........634 chapter 22 reset function .................................................................................................. ......636 22.1 overview .................................................................................................................. ................. 636 22.2 configuration............................................................................................................. ............... 636 preliminary user?s manual u16895ej1v0ud 16 22.3 register to check reset source............................................................................................ . 637 22.4 reset sources ............................................................................................................. ............. 638 22.4.1 reset operatio n via reset pin ........................................................................................... ........ 638 22.4.2 reset operation by wdtres1 signal ....................................................................................... ... 642 22.4.3 reset operation by wdtres2 signal ....................................................................................... ... 643 22.4.4 power-on-clea r reset oper ation.......................................................................................... .......... 644 22.4.5 reset operation by low-voltag e detec tor................................................................................. ..... 647 22.4.6 reset operation by clock monitor........................................................................................ ......... 648 22.5 reset output function..................................................................................................... ........ 649 chapter 23 clock monitor ................................................................................................... ..... 650 23.1 function ....................................................................................................................... ............. 650 23.2 registers ...................................................................................................................... ............. 650 23.3 operation ...................................................................................................................... ............ 652 23.4 ring clock operation mode .................................................................................................... 65 5 23.4.1 setting and oper ation st atus ................................................................................................... ..... 655 23.4.2 releasing ring clo ck operati on mode ........................................................................................... 6 55 23.5 ring halt mode ................................................................................................................. ..... 657 23.5.1 setting and oper ation st atus ................................................................................................... ..... 657 23.5.2 releasing ring halt mode....................................................................................................... ... 657 chapter 24 low-voltage detector ....................................................................................... 659 24.1 function ....................................................................................................................... ............. 659 24.2 configuration.................................................................................................................. .......... 659 24.3 registers ...................................................................................................................... ............. 660 24.4 operation ...................................................................................................................... ............ 662 chapter 25 power-on-clear circuit...................................................................................... 664 25.1 function ....................................................................................................................... ............. 664 25.2 configuration.................................................................................................................. .......... 664 25.3 operation ...................................................................................................................... ............ 665 chapter 26 regulator ........................................................................................................ ......... 666 26.1 overview .................................................................................................................. ................. 666 26.2 operation ................................................................................................................. ................. 666 chapter 27 rom correction function................................................................................. 668 27.1 overview .................................................................................................................. ................. 668 27.2 control registers ......................................................................................................... ............ 669 27.2.1 correction address registers 0 to 3 (corad0 to cora d3) ........................................................ 669 27.2.2 correction contro l register (corcn) ..................................................................................... ...... 670 27.3 rom correction operation and program flow ........... .......................................................... 670 chapter 28 mask option/option byte ................................................................................... 672 28.1 mask option (mask rom versions)................................... ..................................................... 672 28.2 option byte (flash memory versions) ........................... ........................................................ 673 preliminary user?s manual u16895ej1v0ud 17 chapter 29 flash memory.................................................................................................... .......674 29.1 features ....................................................................................................................... ............. 674 29.2 memory configurat ion........................................................................................................... .. 675 29.3 functional outline ............................................................................................................. ...... 676 29.4 rewriting by dedicated flash programmer .............. ............................................................ 678 29.4.1 programming env ironme nt ........................................................................................................ ...678 29.4.2 communicati on m ode............................................................................................................. ......679 29.4.3 flash memory cont rol ........................................................................................................... ........683 29.4.4 selection of co mmunicati on mode................................................................................................ 684 29.4.5 communication comma nds ......................................................................................................... .685 29.4.6 pin con nection ................................................................................................................. .............686 29.5 rewriting by self programming ............................................................................................. 691 29.5.1 overvi ew ....................................................................................................................... ...............691 29.5.2 featur es ....................................................................................................................... ................692 29.5.3 standard self pr ogramming flow ................................................................................................. ..693 29.5.4 flash func tions ................................................................................................................ .............694 29.5.5 pin proc essing ................................................................................................................. .............694 29.5.6 internal res ources used ........................................................................................................ ........695 chapter 30 electrical specifications (target) ..............................................................696 chapter 31 package drawings................................................................................................ .735 appendix a development tools ............................................................................................... 737 a.1 software package ............................................................................................................... ..... 739 a.2 language processing software .................. ........................................................................... 739 a.3 control software ............................................................................................................... ....... 739 a.4 debugging tools (hardware)....................... ........................................................................... 740 a.4.1 when using in-circuit em ulator qb-v 850eskx1 h........................................................................740 a.5 debugging tools (software) ........................................... ........................................................ 74 0 a.6 embedded software .............................................................................................................. .. 741 a.7 flash memory writing tools.......................................... ......................................................... 74 1 appendix b instruction set list........................................................................................... ...742 b.1 conventions .................................................................................................................... ......... 742 b.2 instruction set (in alphabetical or der).................................................................................. 745 appendix c register index .................................................................................................. ........752 preliminary user?s manual u16895ej1v0ud 18 chapter 1 introduction 1.1 k1 family product lineup 1.1.1 v850es/kx1+, v850es/kx1 products lineup v850es/ke1 ? 64-pin plastic lqfp (10 10 mm, 0.5 mm pitch) ? 64-pin plastic tqfp (12 12 mm, 0.65 mm pitch) pd70f3207hy pd70f3207h single-power flash: 128 kb, ram: 4 kb pd703207y pd703207 mask rom: 128 kb, ram: 4 kb pd703210y pd703210 mask rom: 128 kb, ram: 6 kb pd703209y pd703209 mask rom: 96 kb, ram: 4 kb pd70f3210hy pd70f3210h single-power flash: 128 kb, ram: 6 kb pd70f3306y pd70f3306 single-power flash: 128 kb, ram: 6 kb pd70f3210y pd70f3210 two-power flash: 128 kb, ram: 6 kb pd703208y pd703208 mask rom: 64 kb, ram: 4 kb v850es/ke1+ pd70f3302y pd70f3302 single-power flash: 128 kb, ram: 4 kb pd703302y pd703302 mask rom: 128 kb, ram: 4 kb v850es/kf1 ? 80-pin plastic tqfp (12 12 mm, 0.5 mm pitch) ? 80-pin plastic qfp (14 14 mm, 0.65 mm pitch) ? 100-pin plastic lqfp (14 14 mm, 0.5 mm pitch) ? 100-pin plastic qfp (14 20 mm, 0.65 mm pitch) pd70f3211hy pd70f3211h single-power flash: 256 kb, ram: 12 kb pd703211y pd703211 mask rom: 256 kb, ram: 12 kb v850es/kf1+ pd70f3308y pd70f3308 single-power flash: 256 kb, ram: 12 kb pd703308y pd703308 mask rom: 256 kb, ram: 12 kb pd703214y pd703214 mask rom: 128 kb, ram: 6 kb pd703213y pd703213 mask rom: 96 kb, ram: 4 kb pd70f3214hy pd70f3214h single-power flash: 128 kb, ram: 6 kb pd70f3311y pd70f3311 single-power flash: 128 kb, ram: 6 kb pd70f3214y pd70f3214 two-power flash: 128 kb, ram: 6 kb pd703212y pd703212 mask rom: 64 kb, ram: 4 kb v850es/kg1 pd70f3215hy pd70f3215h single-power flash: 256 kb, ram: 16 kb pd703215y pd703215 mask rom: 256 kb, ram: 16 kb v850es/kg1+ pd70f3313y pd70f3313 single-power flash: 256 kb, ram: 16 kb pd703313y pd703313 mask rom: 256 kb, ram: 16 kb ? 144-pin plastic lqfp (20 20 mm, 0.5 mm pitch) pd703217y pd703217 mask rom: 128 kb, ram: 6 kb pd703216y pd703216 mask rom: 96 kb, ram: 6 kb pd70f3217hy pd70f3217h single-power flash: 128 kb, ram: 6 kb pd70f3316y pd70f3316 single-power flash: 128 kb, ram: 6 kb pd70f3217y pd70f3217 two-power flash: 128 kb, ram: 6 kb v850es/kj1 pd70f3218hy pd70f3218h single-power flash: 256 kb, ram: 16 kb v850es/kj1+ pd70f3318y pd70f3318 single-power flash: 256 kb, ram: 16 kb chapter 1 introduction preliminary user?s manual u16895ej1v0ud 19 the function list of the v 850es/kx1+ is shown below. product name v850es/ke1+ v850es/kf1+ v850es/kg1+ v850es/kj1+ number of pins 64 pins 80 pins 100 pins 144 pins mask rom 128 ? ? 256 ? ? 256 ? ? ? flash memory ? 128 128 ? 256 128 ? 256 128 256 internal memory (kb) ram 4 6 12 6 16 6 16 supply voltage 2.7 to 5.5 v minimum instruction execution time 50 ns @20 mhz x1 input 2 to 10 mhz subclock 32.768 khz clock ring-osc 240 khz (typ.) cmos input 8 8 8 16 cmos i/o 43 59 76 112 port n-ch open-drain i/o 2 2 4 6 16-bit (tmp) 1 ch 1 ch 1 ch 1 ch 16-bit (tm0) 1 ch 2 ch 4 ch 6 ch 8-bit (tm5) 2 ch 2 ch 2 ch 2 ch 8-bit (tmh) 2 ch 2 ch 2 ch 2 ch interval timer 1 ch 1 ch 1 ch 1 ch watch 1 ch 1 ch 1 ch 1 ch wdt1 1 ch 1 ch 1 ch 1 ch timer wdt2 1 ch 1 ch 1 ch 1 ch rto 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch csi 2 ch 2 ch 2 ch 3 ch automatic transmit/receive 3-wire csi ? 1 ch 2 ch 2 ch uart 1 ch 1 ch 2 ch 2 ch uart supporting lin-bus 1 ch 1 ch 1 ch 1 ch serial interface i 2 c note 1 ch 1 ch 1 ch 2 ch address space ? 128 kb 3 mb 15 mb address bus ? 16 bits 22 bits 24 bits external bus mode ? multiplex only multiplex/separate dma controller ? ? 4 ch 4 ch 10-bit a/d converter 8 ch 8 ch 8 ch 16 ch 8-bit d/a converter ? ? 2 ch 2 ch external 9 9 9 9 interrupt internal 27 30 42 48 key return input 8 ch 8 ch 8 ch 8 ch reset pin provided poc 2.7 v or less fixed lvi 3.1 v/3.3 v 0.15 v or 3.5 v/3.7 v/3.9 v/4.1 v/4.3 v 0.2 v (selectable by software) clock monitor provided (monitor by ring-osc) wdt1 provided reset wdt2 provided rom correction 4 none regulator none provided standby function halt/idle/stop/sub-idle mode operating ambient temperature t a = ? 40 to +85 c note only in products with an i 2 c bus (y products). for the product name, refer to each user?s manual. chapter 1 introduction preliminary user?s manual u16895ej1v0ud 20 the function list of the v850es/kx1 is shown below. product name v850es/ke1 v850es/kf1 v850es/kg1 v850es/kj1 number of pins 64 pins 80 pins 100 pins 144 pins mask rom 128 ? 64/ 96 128 ? 256 ? 64/ 96 128 ? 256 ? 96/ 128 ? ? flash memory ? 128 ? ? 128 ? 256 ? ? 128 ? 256 ? 128 256 internal memory (kb) ram 4 4 6 12 4 6 16 6 16 supply voltage 2.7 to 5.5 v minimum instruction execution time 50 ns @20 mhz x1 input 2 to 10 mhz subclock 32.768 khz clock ring-osc ? cmos input 8 8 8 16 cmos i/o 43 59 76 112 port n-ch open-drain i/o 2 2 4 6 16-bit (tmp) 1 ch ? 1 ch ? 1 ch ? 1 ch 16-bit (tm0) 1 ch 2 ch 4 ch 6 ch 8-bit (tm5) 2 ch 2 ch 2 ch 2 ch 8-bit (tmh) 2 ch 2 ch 2 ch 2 ch interval timer 1 ch 1 ch 1 ch 1 ch watch 1 ch 1 ch 1 ch 1 ch wdt1 1 ch 1 ch 1 ch 1 ch timer wdt2 1 ch 1 ch 1 ch 1 ch rto 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch csi 2 ch 2 ch 2 ch 3 ch automatic transmit/receive 3-wire csi ? 1 ch 2 ch 2 ch uart 2 ch 2 ch 2 ch 3 ch uart supporting lin-bus ? ? ? ? serial interface i 2 c note 1 ch 1 ch 1 ch 2 ch address space ? 128 kb 3 mb 15 mb address bus ? 16 bits 22 bits 24 bits external bus mode ? multiplex only multiplex/separate dma controller ? ? ? ? 10-bit a/d converter 8 ch 8 ch 8 ch 16 ch 8-bit d/a converter ? ? 2 ch 2 ch external 8 8 8 8 interrupt internal 26 26 29 31 34 40 43 key return input 8 ch 8 ch 8 ch 8 ch reset pin provided poc none lvi none clock monitor none wdt1 provided reset wdt2 provided rom correction 4 regulator none provided standby function halt/idle/stop/sub-idle mode operating ambient temperature t a = ? 40 to +85 c note only in products with an i 2 c bus (y products). for the product name, refer to each user?s manual. chapter 1 introduction preliminary user?s manual u16895ej1v0ud 21 1.1.2 78k0/kx1+, 78k0/kx1 products lineup mask rom: 24 kb, ram: 768 b mask rom: 16 kb, ram: 768 b mask rom: 8 kb, ram: 512 b pd780101 78k0/kb1 30-pin ssop (7.62 mm 0.65 mm pitch) single-power flash: 24 kb, ram: 768 b single-power flash: 16 kb, ram: 768 b single-power flash: 8 kb, ram: 512 b pd780102 pd780103 pd78f0103 two-power flash: 24 kb, ram: 768 b 78k0/kb1+ pd78f0102h pd78f0103h pd78f0101h 44-pin lqfp (10 10 mm 0.8 mm pitch) pd78f0114 two-power flash: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb pd780114 mask rom: 24 kb, ram: 1 kb pd780113 mask rom: 16 kb, ram: 512 b pd780112 pd780111 78k0/kc1 single-power flash: 32 kb, ram: 1 kb single-power flash: 24 kb, ram: 1 kb single-power flash: 16 kb, ram: 512 b 78k0/kc1+ pd78f0113h pd78f0114h/hd note pd78f0112h mask rom: 8 kb, ram: 512 b pd78f0124 mask rom: 32 kb, ram: 1 kb pd780124 mask rom: 24 kb, ram: 1 kb pd780123 mask rom: 16 kb, ram: 512 b pd780122 mask rom: 8 kb, ram: 512 b pd780121 52-pin lqfp (10 10 mm 0.65 mm pitch) single-power flash: 32 kb, ram: 1 kb single-power flash: 24 kb, ram: 1 kb single-power flash: 16 kb, ram: 512 b 78k0/kd1+ pd78f0123h pd78f0124h/hd note pd78f0122h 78k0/kd1 two-power flash: 32 kb, ram: 1 kb pd78f0148 mask rom: 60 kb, ram: 2 kb pd780148 mask rom: 48 kb, ram: 2 kb pd780146 mask rom: 32 kb, ram: 1 kb pd780144 mask rom: 24 kb, ram: 1 kb pd780143 80-pin tqfp, qfp (12 12 mm 0.5 mm pitch, 14 14 mm 0.65 mm pitch) single-power flash: 60 kb, ram: 2 kb 78k0/kf1+ pd78f0148h/hd note 78k0/kf1 flash memory: 60 kb, ram: 2 kb pd78f0138 pd780138 pd780136 64-pin lqfp, tqfp (10 10 mm 0.5 mm pitch, 12 12 mm 0.65 mm pitch, 14 14 mm 0.8 mm pitch) 78k0/ke1+ pd78f0136h pd78f0138h/hd note 78k0/ke1 pd78f0134 mask rom: 32 kb, ram: 1 kb pd780134 mask rom: 24 kb, ram: 1 kb pd780133 mask rom: 16 kb, ram: 512 b pd780132 mask rom: 8 kb, ram: 512 b pd780131 single-power flash: 32 kb, ram: 1 kb single-power flash: 24 kb, ram: 1 kb single-power flash: 16 kb, ram: 512 b pd78f0133h pd78f0134h pd78f0132h flash memory: 32 kb, ram: 1 kb mask rom: 60 kb, ram: 2 kb mask rom: 48 kb, ram: 2 kb single-power flash: 60 kb, ram: 2 kb single-power flash: 48 kb, ram: 2 kb flash memory: 60 kb, ram: 2 kb note products with an on-chip debug function chapter 1 introduction preliminary user?s manual u16895ej1v0ud 22 the function list of the 78k 0/kx1+ is shown below. product name item 78k0/kb1+ 78k0/kc1+ 78k0/kd1+ 78k0/ke1+ 78k0/kf1+ number of pins 30 pins 44 pins 52 pins 64 pins 80 pins flash memory 8 k 16 k/24 k 16 k 24 k/32 k 16 k 24 k/32 k 16 k 24 k/ 32 k 48 k/ 60 k 60 k internal memory (byte) ram 512 768 512 1 k 512 1 k 512 1 k 2 k 2 k supply voltage v dd = 2.7 to 5.5 v minimum instruction execution time 0.125 s (16 mhz, when v dd = 4.0 to 5.5 v) 0.24 s (8.38 mhz, when v dd = 3.3 to 5.5 v) 0.4 s (5 mhz, when v dd = 2.7 to 5.5 v) x1 input 2 to 16 mhz rc 3 to 4 mhz (v dd = 2.7 to 5.5 v) ? sub ? 32.768 khz clock ring-osc 240 khz (typ.) cmos i/o 17 19 26 38 54 cmos input 4 8 cmos output 1 port n-ch open-drain i/o ? 4 16-bit (tm0) 1 ch 2 ch 8-bit (tm5) 2 ch 8-bit (tmh) 1 ch 2 ch watch ? 1 ch timer wdt 1 ch 3-wire csi note 1 ch 2 ch automatic transmit/ receive 3-wire csi ? 1 ch uart note ? 1 ch serial interface uart supporting lin-bus 1 ch 10-bit a/d converter 4 ch 8 ch external 6 7 8 9 9 interrupt internal 11 12 15 15 16 19 20 key return input ? 4 ch 8 ch reset pin provided poc 2.1 v 0.1 v (detection voltage fixed) lvi 2.35 v/2.6 v/2.85 v/3.1 v/3.3 v 0.15 v/3.5 v/3.7 v/3.9 v/4.1 v/4.3 v 0.2 v (selectable by software) clock monitor provided reset wdt provided clock output/buzzer output ? clock output only provided external bus interface ? provided multiplier/divider ? 16 bits 16 bits, 32 bits 16 bits rom correction ? provided ? self programming function provided on-chip debug function function provided only in pd78f0114hd, 78f0124hd, 78f0138hd, and 78f0148hd standby function halt/stop mode operating ambient temperature ? 40 to +85 c note if the pin is an alternate-function pin, either function is selected for use. chapter 1 introduction preliminary user?s manual u16895ej1v0ud 23 the function list of the 78k0/kx1 is shown below. product name item 78k0/kb1 78k0/kc1 78k0/ kd1 78k0/ke1 78k0/kf1 number of pins 30 pins 44 pi ns 52 pins 64 pins 80 pins mask rom 8 k 16 k/ 24 k ? 8 k/ 16 k 24 k/ 32 k ? 8 k/ 16 k 24 k/ 32 k ? 8 k/ 16 k 24 k/ 32 k ? 48 k/ 60 k ? 24 k/ 32 k 48 k/ 60 k ? flash memory ? 24 k ? 32 k ? 32 k ? 32 k ? 60 k ? 60 k internal memory (byte) ram 512 768 512 1 k 512 1 k 512 1 k 2 k 1 k 2 k supply voltage v dd = 2.7 to 5.5 v minimum instruction execution time 0.2 s (10 mhz, when v dd = 4.0 to 5.5 v) 0.24 s (8.38 mhz, when v dd = 3.3 to 5.5 v) 0.4 s (5 mhz, when v dd = 2.7 to 5.5 v) chapter 1 introduction preliminary user?s manual u16895ej1v0ud 24 1.2 features { minimum instruction execution time: 50 ns (operation at main clock (f xx ) = 20 mhz) { general-purpose registers: 32 bits 32 registers { cpu features: signed multiplication (16 16 32): 1 to 2 clocks (instructions without creating register haza rds can be continuously executed in parallel) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space memory block division function : 64 kb, 64 kb (total of 2 blocks) ? internal memory pd703308, 703308y (mask rom: 256 kb/ram: 12 kb) pd70f3306, 70f3306y (single-power flash memory: 128 kb/ram: 6 kb) pd70f3308, 70f3308y (single-power flash memory: 256 kb/ram: 12 kb) ? external bus interface multiplex bus output 8-/16-bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function { interrupts and exceptions non-maskable interrupts: 3 sources maskable interrupts: 35 sources ( pd703308, 70f3306, 70f3308) 36 sources ( pd703308y, 70f3306y, 70f3308y) software exceptions: 32 sources exception trap: 1 source { i/o lines: total: 67 { key interrupt function { timer function 16-bit timer/event counter p: 1 channel 16-bit timer/event counter 0: 2 channels 8-bit timer/event counter 5: 2 channels 8-bit timer h: 2 channels 8-bit interval timer brg: 1 channel watch timer/interval timer: 1 channel watchdog timers watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel watchdog timer 2: 1 channel chapter 1 introduction preliminary user?s manual u16895ej1v0ud 25 { serial interface asynchronous serial interface (uart) (supporting lin): 1 channel asynchronous serial interface (uart): 1 channel 3-wire serial i/o (csi0): 2 channels 3-wire serial i/o (with automatic trans mit/receive function) (csia): 1 channel i 2 c bus interface (i 2 c): 1 channel ( pd703308y, 70f3306y, 70f3308y) { a/d converter: 10-bit resolution 8 channels { real-time output port: 6 bits 1 channel { standby functions: halt/idle/stop modes, subclock/sub- idle modes, ring clock operation/ring halt modes { rom correction: 4 correction addresses specifiable { clock generator main clock oscillation (f x )/subclock oscillation (f xt )/ring-osc (f r ) cpu clock (f cpu ) 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { ring-osc: 240 khz (typ.) { reset ? reset by reset pin ? reset by overflow of watchdog timer 1 (wdtres1) ? reset by overflow of watchdog timer 2 (wdtres2) ? reset by low-voltage detector (lvires) ? reset by power-on-clear (pocres) ? reset by clock monitor (clmres) ? reset output function (p00/toh0 pin) { low-voltage detector (lvi) { power-on-clear (poc) circuit { clock monitor (clm) circuit { package: 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) chapter 1 introduction preliminary user?s manual u16895ej1v0ud 26 1.3 applications { automotive ? system control of body electrical system (p ower windows, keyless entry reception, etc.) ? submicrocontroller of control system { home audio, car audio { av equipment { pc peripheral devices (keyboards, etc.) { household appliances ? outdoor units of air conditioners ? microwave ovens, rice cookers { industrial devices ? pumps ? vending machines ? fa 1.4 ordering information part number package quality grade pd703308gk- -9eu pd703308ygk- -9eu pd703308gc- -8bt pd703308ygc- -8bt pd70f3306gk-9eu pd70f3306ygk-9eu pd70f3306gc-8bt pd70f3306ygc-8bt pd70f3308gk-9eu pd70f3308ygk-9eu pd70f3308gc-8bt pd70f3308ygc-8bt 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) standard standard standard standard standard standard standard standard standard standard standard standard remark indicates rom code suffix. chapter 1 introduction preliminary user?s manual u16895ej1v0ud 27 1.5 pin configuration (top view) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) pd703308gc- -8bt pd703308ygc- -8bt pd703308gk- -9eu pd703308ygk- -9eu pd70f3306gc-8bt pd70f3306ygc-8bt pd70f3306gk-9eu pd70f3306ygk-9eu pd70f3308gc-8bt pd70f3308ygc-8bt pd70f3308gk-9eu pd70f3308ygk-9eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 av ref0 av ss p00/toh0 p01/toh1 p02/nmi p03/intp0 p04/intp1 flmd0 note 1 /ic note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p05/intp2 p06/intp3 p40/si00 p41/so00 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs1/cs1 pcs0/cs0 p915/intp6 p914/intp5 p913/intp4 p99/sck01 p98/so01 p97/si01 p42/sck00 p30/txd0 p31/rxd0/intp7 p32/asck0/adtrg/to01 p33/ti000/to00/tip00/top00 p34/ti001/to00/tip01/top01 p35/ti010/to01 p38/sda0 note 3 p39/scl0 note 3 ev ss ev dd p50/ti011/rtp00/kr0 p51/ti50/rtp01/kr1 p52/to50/rtp02/kr2 p53/sia0/rtp03/kr3 p54/soa0/rtp04/kr4 p55/scka0/rtp05/kr5 p90/txd1/kr6 p91/rxd1/kr7 p96/ti51/to51 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 note 1 pdl4/ad4 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 notes 1. ic pin: connect directly to v ss ( pd703308, 703308y). flmd0 pin: connect to v ss in normal operation mode ( pd70f3306, 70f3306y, 70f3308, 70f3308y). flmd1 pin: used only in the pd70f3306, 70f3306y, 70f3308, and 70f3308y. 2. when using a regulator, connect the regc pin to v ss via a 10 f capacitor. when not using a regulator, connect the regc pin directly to v dd . 3. the scl0 and sda0 pins can be used only in the pd703308y, 70f3306y, and 70f3308y. caution make ev dd the same potential as v dd . chapter 1 introduction preliminary user?s manual u16895ej1v0ud 28 pin identification ad0 to ad15: adtrg: ani0 to ani7: asck0: astb: av ref0 : av ss : clkout: cs0, cs1: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: ic: intp0 to intp7: kr0 to kr7: nmi: p00 to p06: p30 to p35, p38, p39: p40 to p42: p50 to p55: p70 to p77: p90, p91, p96 to p99, p913 to p915: pcm0 to pcm3: pcs0, pcs1: pct0, pct1, pct4, pct6: address/data bus a/d trigger input analog input asynchronous serial clock address strobe analog reference voltage ground for analog clock output chip select power supply for port ground for port flash programming mode hold acknowledge hold request internally connected external interrupt input key return non-maskable interrupt request port 0 port 3 port 4 port 5 port 7 port 9 port cm port cs port ct pdl0 to pdl15: rd: regc: reset: rtp00 to rtp05: rxd0, rxd1: sck00, sck01, scka0: scl0: sda0: si00, si01, sia0: so00, so01, soa0: ti000, ti001, ti010, ti011, ti50, ti51, tip00, tip01: to00, to01, to50, to51, toh0, toh1, top00, top01: txd0, txd1: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port dl read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction preliminary user?s manual u16895ej1v0ud 29 1.6 function block configuration (1) internal block diagram nmi to00, to01 ti000, ti001, ti010, ti011 so00, so01 si00, si01 sck00, sck01 intp0 to intp7 top00, top01 tip00, tip01 to50, to51 ti50, ti51 toh0, toh1 txd0, txd1 rxd0, rxd1 asck0 rtp00 to rtp05 kr0 to kr7 rto: 1 ch sda0 note 3 scl0 note 3 clm ring-osc ram rom pc alu cpu hldrq hldak astb rd wait wr0, wr1 cs0, cs1 ad0 to ad15 pdl0 to pdl15 pct0, pct1, pct4, pct6 pcs0, pcs1 pcm0 to pcm3 p70 to p77 p50 to p55 p40 to p42 p30 to p35, p38, p39 p00 to p06 av ref0 av ss ani0 to ani7 adtrg ic note 4 ev dd ev ss flmd0, flmd1 note 5 v ss bcu soa0 sia0 scka0 poc lvi regulator cg clkout x1 x2 xt1 xt2 reset v dd v ss regc intc 16-bit timer/event counter 0: 2 ch 16-bit timer/ event counter p: 1 ch 8-bit timer/event counter 5: 2 ch 8-bit timer h: 2 ch note 1 note 2 rom correction general-purpose registers 32 bits 32 multiplier 16 16 32 system registers 32-bit barrel shifter instruction queue port a/d converter key interrupt function watchdog timer: 2 ch watch timer uart : 2 ch csia: 1 ch i 2 c note 3 : 1 ch csi0: 2 ch p90, p91, p96 to p99, p913 to p915 notes 1. pd703308, 703308y: 256 kb (mask rom) pd70f3306, 70f3306y: 128 kb (flash memory) pd70f3308, 70f3308y: 256 kb (flash memory) 2. pd70f3306, 70f3306y: 6 kb pd703308, 703308y, 70f3308, 70f3308y: 12 kb 3. only in the pd703308y, 70f3306y, 70f3308y 4. only in the pd703308, 703308y 5. only in the pd70f3306, 70f3306y, 70f3308, 70f3308y chapter 1 introduction preliminary user?s manual u16895ej1v0ud 30 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate complex processing. (b) bus control unit (bcu) the bcu starts a required external bus cycle bas ed on the physical address obtained by the cpu. when an instruction is fetched from external memo ry area and the cpu does not send a bus cycle start request, the bcu generates a prefet ch address and prefetches the inst ruction code. the prefetched instruction code is stored in an internal instruction queue. (c) rom this consists of a 256 kb or 128 kb mask rom or flash memory mapped to the address spaces from 0000000h to 003ffffh or 0000000h to 001ffffh, respectively. rom can be accessed by the cpu in one cl ock cycle during instruction fetch. (d) ram this consists of a 12 kb or 6 kb ram mapped to t he address spaces from 3ffc000h to 3ffefffh or 3ffd800h to 3ffefffh. ram can be accessed by the cpu in on e clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp7) from on-chip peripheral hardware and external hardware. eight levels of inte rrupt priorities can be spec ified for these interrupt requests, and multiplexed servicing control can be performed. (f) clock generator (cg) a main clock oscillator and subclock oscillator ar e provided and generate the main clock oscillation frequency (f x ) and subclock frequency (f xt ), respectively. there are two modes: in the clock-through mode, f x is used as the main clock frequency (f xx ) as is. in the pll mode, f x is used multiplied by 4. the cpu clock frequency (f cpu ) can be selected from among f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (g) timer/counter two 16-bit timer/event counter 0 channels, one 16-b it timer/event counter p channel, and two 8-bit timer/event counter 5 channels ar e incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. two 8-bit timer/event counter 5 channels can be connec ted in cascade to configure a 16-bit timer. two 8-bit timer h channels enabling programmable pulse output are provided on chip. chapter 1 introduction preliminary user?s manual u16895ej1v0ud 31 (h) watch timer this timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 khz) or f brg (32.768 khz) from the clock generator. at t he same time, the watch timer can be used as an interval timer. (i) watchdog timer two watchdog timer channels are provided on chip to detect program loops and system abnormalities. watchdog timer 1 can be used as an interval timer. when used as a watchdog timer, it generates a non- maskable interrupt request signal (intwdt1) or system reset signal (wdtres1) after an overflow occurs. when used as an interval timer, it generates a mask able interrupt request signal (intwdtm1) after an overflow occurs. watchdog timer 2 operates by default following reset release. it generates a non-maskable interrupt request signal (intwdt2) or system rese t signal (wdtres2) after an overflow occurs. (j) serial interface (sio) the v850es/kf1+ includes four kinds of serial in terfaces: an asynchronous serial interface (uartn) (supporting 1-channel lin), a clocked serial interface (csi0n), a clocked serial interface with an automatic transmit/receive function (csia0), and an i 2 c bus interface (i 2 c0), and can simultaneously use up to six channels. for uartn, data is transferred via the txdn and rxdn pins. for csi0n, data is transferred via the so0n, si0n, and sck0n pins. for csia0, data is transferred via the soa0, sia0, and scka0 pins. for i 2 c0, data is transferred via the sda0 and scl0 pins. i 2 c0 is provided only in the pd703308y, 70f3306y, and 70f3308y. remark n = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 8 analog input pins. conversion is performed using the successive approximation method. (l) rom correction this function is used to replace part of a program in the mask rom with that contained in the internal ram. up to four correction addresses can be specified. (m) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins. (n) real-time output function this function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. a 1-channel 6-bit data real-time out put function is provided on chip. chapter 1 introduction preliminary user?s manual u16895ej1v0ud 32 (o) clock monitor the clock monitor samp les the main clock (f x ) using the on-chip ring-osc clock (f r ), and generates a reset request signal when the oscillat ion of the main clock is stopped. (p) low-voltage detector (lvi) the low-voltage detector com pares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal interrupt signal or internal reset signal when v dd < v lvi . (q) power-on-clear (poc) circuit the power-on-clear circuit generates an internal reset signal at power on. the power-on-clear circuit compares the supply voltage (v dd ) and detection voltage (v poc ), and generates an internal reset signal when v dd < v poc . (r) ports as shown below, the following ports have general-p urpose port functions and control pin functions. port i/o alternate function p0 7-bit i/o nmi, external interrupt, timer output p3 8-bit i/o serial interface, timer i/o, external interrupt, a/d converter trigger p4 3-bit i/o serial interface p5 6-bit i/o serial interface, timer i/o, ke y interrupt function, real-time output function p7 8-bit input a/d converter analog input p9 9-bit i/o serial interface, timer i/o, external interrupt, key interrupt function pcm 4-bit i/o external bus control signal pcs 2-bit i/o chip select output pct 4-bit i/o external bus control signal pdl 16-bit i/o external address/data bus chapter 1 introduction preliminary user?s manual u16895ej1v0ud 33 1.7 overview of functions part number pd703308/ pd703308y pd70f3306/ pd70f3306y pd70f3308/ pd70f3308y rom 256 kb 128 kb (single-power flash memory) 256 kb (single-power flash memory) internal memory high-speed ram 12 kb 6 kb 12 kb buffer ram 32 bytes logical space 64 mb memory space external memory area 128 kb external bus interface address/data bus: 16 multiplex bus mode general-purpose registers 32 bits 32 registers ceramic/crystal/external clock when pll not used 2 to 8 mhz note 1 : 2.7 to 5.5 v regc pin connected directly to v dd 2 to 5 mhz: 4.5 to 5.5 v, 2 mhz: 2.7 to 5.5 v main clock (oscillation frequency) when pll used 10 f capacitor connected to regc pin 2 mhz: 4.0 to 5.5 v subclock (oscillation frequency) crystal/external clock (32.768 khz) minimum instruction execution time 50 ns (when main clock operated at (f xx ) = 20 mhz) dsp function 32 32 = 64: 200 to 250 ns (at 20 mhz) 32 32 + 32 = 32: 300 ns (at 20 mhz) 16 16 = 32: 50 to 100 ns (at 20 mhz) 16 16 + 32 = 32: 150 ns (at 20 mhz) i/o ports 67 ? input: 8 ? i/o: 59 (among these, n-ch open-drain output selectable: 6, fixed to n-ch open-drain output: 2) timer 16-bit timer/event counter p: 1 channel 16-bit timer/event counter 0: 2 channels 8-bit timer/event counter 5: 2 channels (16-bit timer/event counter: usable as 1 channel) 8-bit timer h: 2 channels watchdog timer: 2 channels watch timer: 1 channel 8-bit interval timer: 1 channel real-time output port 4 bits 1, 2 bits 1, or 6 bits 1 a/d converter 10-bit resolution 8 channels serial interface csi: 2 channels csia (with automatic transmi t/receive function): 1 channel uart (supporting lin): 1 channel uart: 1 channel i 2 c bus: 1 channel note 2 dedicated baud rate generator: 2 channels interrupt sources external: 10 (10) note 3 , internal: 30 note 2 /29 power save function stop/idle/halt/sub-idle mode operating supply voltage 4.5 to 5.5 v (a t 20 mhz)/2.7 to 5.5 v (at 8 mhz) package 80-pin plastic tqfp (fine pitch) (12 12 mm) 80-pin plastic qfp (14 14 mm) notes 1. these values may change after evaluation. 2. only in the pd703308y, 70f3306y, 70f3308y 3. the figure in parentheses indica tes the number of external inte rrupts for which stop mode can be released. preliminary user?s manual u16895ej1v0ud 34 chapter 2 pin functions the names and functions of the pins of the v850es/kf1+ are described below, divided into port pins and non-port pins. the pin i/o buffer power supplies ar e divided into two systems; av ref0 and ev dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 ev dd reset, ports 0, 3 to 5, 9, cm, cs, ct, dl 2.1 list of pin functions (1) port pins (1/3) pin name pin no. i/o pull-up resistor function alternate function p00 3 toh0 p01 4 toh1 p02 5 nmi p03 6 intp0 p04 7 intp1 p05 17 intp2 p06 18 i/o yes port 0 i/o port input/output can be specified in 1-bit units. intp3 p30 25 txd0 p31 26 rxd0/intp7 p32 27 asck0/adtrg/to01 p33 28 ti000/to00/tip00/top00 p34 29 ti001/to00/tip01/top01 p35 30 yes ti010/to01 p38 35 sda0 note 2 p39 36 i/o no note 1 port 3 i/o port input/output can be specified in 1-bit units. p38 and p39 are fixed to n-ch open-drain output. scl0 note 2 p40 22 si00 p41 23 so00 p42 24 i/o yes port 4 i/o port input/output can be specified in 1-bit units. p41 and p42 can be specified as n-ch open- drain output in 1-bit units. sck00 notes 1. an on-chip pull-up resistor can be provided by a mask option (only in the pd703308, 703308y). 2. only in the pd703308y, 70f3306y, 70f3308y chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 35 (2/3) pin name pin no. i/o pull-up resistor function alternate function p50 37 ti011/rtp00/kr0 p51 38 ti50/rtp01/kr1 p52 39 to50/rtp02/kr2 p53 40 sia0/rtp03/kr3 p54 41 soa0/rtp04/kr4 p55 42 i/o yes port 5 i/o port input/output can be specified in 1-bit units. p54 and p55 can be specified as n-ch open- drain output in 1-bit units. scka0/rtp05/kr5 p70 80 ani0 p71 79 ani1 p72 78 ani2 p73 77 ani3 p74 76 ani4 p75 75 ani5 p76 74 ani6 p77 73 input no port 7 input port ani7 p90 38 txd1/kr6 p91 39 rxd1/kr7 p96 40 ti51/to51 p97 41 si01 p98 42 so01 p99 43 sck01 p913 44 intp4 p914 45 intp5 p915 46 i/o yes port 9 i/o port input/output can be specified in 1-bit units. p98 and p99 can be specified as n-ch open- drain output in 1-bit units. intp6 pcm0 49 wait pcm1 50 clkout pcm2 51 hldak pcm3 52 i/o yes port cm i/o port input/output can be specified in 1-bit units. hldrq pcs0 47 cs0 pcs1 48 i/o yes port cs i/o port input/output can be specified in 1-bit units. cs1 pct0 53 wr0 pct1 54 wr1 pct4 55 rd pct6 56 i/o yes port ct i/o port input/output can be specified in 1-bit units. astb chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 36 (3/3) pin name pin no. i/o pull-up resistor function alternate function pdl0 57 ad0 pdl1 58 ad1 pdl2 59 ad2 pdl3 60 ad3 pdl4 61 ad4 pdl5 62 ad5/flmd1 note pdl6 63 ad6 pdl7 64 ad7 pdl8 65 ad8 pdl9 66 ad9 pdl10 67 ad10 pdl11 68 ad11 pdl12 69 ad12 pdl13 70 ad13 pdl14 71 ad14 pdl15 72 i/o yes port dl i/o port input/output can be specified in 1-bit units. ad15 note only in the pd70f3306, 70f3306y, 70f3308, 70f3308y chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 37 (2) non-port pins (1/3) pin name pin no. i/o pull-up resistor function alternate function ad0 57 pdl0 ad1 58 pdl1 ad2 59 pdl2 ad3 60 pdl3 ad4 61 pdl4 ad5 62 pdl5/flmd1 note ad6 63 pdl6 ad7 64 pdl7 ad8 65 pdl8 ad9 66 pdl9 ad10 67 pdl10 ad11 68 pdl11 ad12 69 pdl12 ad13 70 pdl13 ad14 71 pdl14 ad15 72 i/o yes address/data bus for external memory pdl15 adtrg 24 input yes a/d converter external trigger input p32/asck0/to01 ani0 80 p70 ani1 79 p71 ani2 78 p72 ani3 77 p73 ani4 76 p74 ani5 75 p75 ani6 74 p76 ani7 73 input no analog voltage input for a/d converter p77 asck0 24 input yes uart0 serial clock input p32/adtrg/to01 astb 56 output yes address strobe signal output for external memory pct6 av ref0 1 ? ? reference voltage for a/d converter and positive power supply for alternate-function ports ? av ss 2 ? ? ground potential for a/d converter and alternate-function ports ? clkout 50 output yes internal system clock output pcm1 cs0 47 pcs0 cs1 48 output yes chip select output pcs1 ev dd 31 ? ? positive power supply for external ? ev ss 30 ? ? ground potential for external ? flmd0 note 8 no ? flmd1 note 62 input yes flash programming mode setting pin pdl5/ad5 hldak 51 output yes bus hold acknowledge output pcm2 hldrq 52 input yes bus hold request input pcm3 note only in the pd70f3306, 70f3306y, 70f3308, 70f3308y chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 38 (2/3) pin name pin no. i/o pull-up resistor function alternate function ic note 1 8 ? ? internally connected ? intp0 6 p03 intp1 7 p04 intp2 17 external interrupt request input (maskable, analog noise elimination) p05 intp3 18 external interrupt request input (maskable, digital + anal og noise elimination) p06 intp4 44 p913 intp5 45 p914 intp6 46 p915 intp7 23 input yes external interrupt request input (maskable, analog noise elimination) p31/rxd0 kr0 32 p50/ti011/rtp00 kr1 33 p51/ti50/rtp01 kr2 34 p52/to50/rtp02 kr3 35 p53/sia0/rtp03 kr4 36 p54/soa0/rtp04 kr5 37 p55/scka0/rtp05 kr6 38 p90/txd1 kr7 39 input yes key return input p91/rxd1 nmi 5 input yes external interrupt input (non-maskable, analog noise elimination) p02 rd 55 output yes read strobe signal output for external memory pct4 regc 10 ? ? connecting capacitor for regulator output stabilization ? reset 14 input ? system reset input ? rtp00 32 p50/ti011/kr0 rtp01 33 p51/ti50/kr1 rtp02 34 p52/to50/kr2 rtp03 35 p53/sia0/kr3 rtp04 36 p54/soa0/kr4 rtp05 37 output yes real-time output port p55/scka0/kr5 rxd0 23 serial receive data input for uart0 p31/intp7 rxd1 39 input yes serial receive data input for uart1 p91/kr7 sck00 21 p42 sck01 43 p99 scka0 37 i/o yes serial clock i/o for cs i00, csi01, csia0 n-ch open-drain output can be specified in 1- bit units. p55/rtp05/kr5 scl0 note 2 29 i/o no note 3 serial clock i/o for i 2 c0 fixed to n-ch open-drain output p39 sda0 note 2 28 i/o no note 3 serial transmit/receive data i/o for i 2 c0 fixed to n-ch open-drain output p38 notes 1. only in the pd703308, 703308y 2. only in the pd703308y, 70f3306y, 70f3308y 3. an on-chip pull-up resistor can be provided by a mask option (only in the pd703308y). chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 39 (3/3) pin name pin no. i/o pull-up resistor function alternate function si00 19 serial receive data input for csi00 p40 si01 41 serial receive data input for csi01 p97 sia0 35 input yes serial receive data input for csia0 p53/rtp03/kr3 so00 20 p41 so01 42 p98 soa0 36 output yes serial transmit data output for csi00, csi01, csia0 n-ch open-drain output can be specified in 1- bit units. p54/rtp04/kr4 ti000 25 capture trigger input/external event input for tm00 p33/to00/tip00/top00 ti001 26 capture trigger input for tm00 p34/to00/tip01/top01 ti010 27 capture trigger input/external event input for tm01 p35/to01 ti011 32 capture trigger input for tm01 p50/rtp00/kr0 ti50 33 external event input for tm50 p51/rtp01/kr1 ti51 40 external event input for tm51 p96/to51 tip00 25 capture trigger input/external event input for tmp0 p33/ti000/to00/top00 tip01 26 input yes capture trigger input for tmp0 p34/ti001/to00/top01 25 p33/ti000/tip00/top00 to00 26 timer output for tm00 p34/ti001/tip01/top01 24 p32/asck0/adtrg to01 27 timer output for tm01 p35/ti010 to50 34 timer output for tm50 p52/rtp02/kr2 to51 40 timer output for tm51 p96/ti51 toh0 3 timer output for tmh0 p00 toh1 4 timer output for tmh1 p01 top00 25 p33/ti000/to00/tip00 top01 26 output yes timer output for tmp0 p34/ti001/to00/tip01 txd0 22 serial transmit data output for uart0 p30/to02 txd1 38 output yes serial transmit data output for uart1 p90/kr6 v dd 9 ? ? positive power s upply pin for internal ? v ss 11 ? ? ground potential for internal ? wait 49 input no external wait input pcm0 wr0 53 write strobe for external memory (lower 8 bits) pct0 wr1 54 output no write strobe for external memory (higher 8 bits) pct1 x1 12 input no ? x2 13 ? no connecting resonator for main clock ? xt1 15 input no ? xt2 16 ? no connecting resonator for subclock ? chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 40 2.2 pin status the address bus becomes undefined during accesses to the internal ram and rom. the data bus goes into the high-impedance state without data output. the external bus control signal becomes inactive. during peripheral i/o access, the address bus outputs t he addresses of the on-chip peripheral i/os that are accessed. the data bus goes into t he high-impedance state without data output. the external bus control signal becomes inactive. table 2-2. pin operation status in operation modes operating status pin reset note 1 halt mode idle mode/ stop mode idle state note 2 bus hold ad0 to ad15 (pdl0 to pdl15) hi-z undefined hi-z held hi-z wait (pcm0) hi-z ? ? ? ? clkout (pcm1) hi-z operat ing l operating operating cs0, cs1 (pcs0, pcs1) hi-z h h held hi-z wr0, wr1 (pct0, pct1) hi-z h h h hi-z rd (pct4) hi-z h h h hi-z astb (pct6) hi-z h h h hi-z hldak (pcm2) hi-z operating h h l hldrq (pcm3) hi-z o perating ? ? operating notes 1. since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. the pin statuses in the idle state inserted after the t3 state are listed. remark hi-z: high impedance h: high-level output l: low-level output ?: input without sampling (in put acknowledgment not possible) chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 41 2.3 pin i/o circuits and recommend ed connection of unused pins (1/2) pin alternate function pin no. i/o circuit type recommended connection p00 toh0 3 p01 toh1 4 5-a p02 nmi 5 p03 to p06 intp0 to intp3 6, 7, 17, 18 5-w p30 txd0 22 5-a p31 rxd0/intp7 23 p32 asck0/adtrg/to01 24 p33 ti000/to00/tip00/top00 25 p34 ti001/to00/tip01/top01 26 p35 ti010/to01 27 5-w p38 sda0 note 28 p39 scl0 note 29 13-ae p40 si00 19 5-w p41 so00 20 10-e p42 sck00 21 10-f p50 ti011/rtp00/kr0 32 p51 ti50/rtp01/kr1 33 p52 to50/rtp02/kr2 34 p53 sia0/rtp03/kr3 35 8-a p54 soa0/rtp04/kr4 36 p55 scka0/rtp05/kr5 37 10-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. p70 to p77 ani0 to ani7 80 to 73 9-c connect to av ref0 or av ss . p90 txd1/kr6 38 p91 rxd1/kr7 39 8-a p96 ti51/to51 40 8-a p97 si01 41 5-w p98 so01 42 10-e p99 sck01 43 10-f p913 to p915 intp4 to intp6 44 to 46 5-w pcm0 wait 49 pcm1 clkout 50 pcm2 hldak 51 pcm3 hldrq 52 5-a pcs0, pcs1 cs0, cs1 47, 48 5-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. note only in the chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 42 (2/2) pin alternate function pin no. i/o circuit type recommended connection pct0 wr0 53 pct1 wr1 54 pct4 rd 55 pct6 astb 56 5-a pdl0 to pdl4 ad0 to ad4 57 to 61 pdl5 ad5/flmd1 note 1 62 pdl6 to pdl15 ad6 to ad15 63 to 72 5-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. av ref0 ? 1 ? directly connect to v dd . av ss ? 2 ? ? ev dd ? 31 ? ? ev ss ? 30 ? ? ic note 2 ? 8 ? directly connect to ev ss or v ss or pull down with a 10 k ? resistor. reset ? 14 2 ? flmd0 note 1 ? 8 ? directly connect to ev ss or v ss or pull down with a 10 k ? resistor. v dd ? 9 ? ? v ss ? 11 ? ? x1 ? 12 ? ? x2 ? 13 ? ? xt1 ? 15 16 directly connect to v ss note 3 . xt2 ? 16 16 leave open. notes 1. only in the pd70f3306, 70f3306y, 70f3308, 70f3308y 2. only in the pd703308, 703308y 3. be sure to set the psmr.xtstp bit to 1 when this pin is not used. chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 43 2.4 pin i/o circuits (1/2) type 2 type 9-c type 5-a type 10-a type 5-w type 10-e type 8-a type 10-f schmitt-triggered input with hysteresis characteristics in data output disable p-ch in/out v dd n-ch input enable p-ch v dd pull-up enable in comparator + ? av ref0 (threshold voltage) p-ch av ss n-ch input enable pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch data output disable v dd p-ch in/out n-ch open drain pull-up enable v dd p-ch data output disable v dd p-ch in/out n-ch open drain input enable pull-up enable v dd p-ch pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch data output disable v dd p-ch in/out n-ch open drain input enable pull-up enable v dd p-ch v ss v ss v ss v ss v ss v ss chapter 2 pin functions preliminary user?s manual u16895ej1v0ud 44 (2/2) type 13-ae type 16 p-ch feedback cut-off xt1 xt2 data output disable input enable in/out n -ch v ss mask option v dd remark read v dd as ev dd . also, read v ss as ev ss . preliminary user?s manual u16895ej1v0ud 45 chapter 3 cpu functions the cpu of the v850es/kf1+ is based on the risc architecture and executes most instructions in one clock cycle by using 5-stage pipeline control. 3.1 features { number of instructions: 83 { minimum instruction execution time: 50.0 ns (@ 20 mhz operation: 4.5 to 5.5 v, not using regulator) 125 ns note (@ 8 mhz operation: 2.7 to 5.5 v, not using regulator) { memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear ? memory block division function: 64 kb, 64 kb/total of 2 blocks { general-purpose registers: 32 bits 32 { internal 32-bit architecture { 5-stage pipeline control { multiply/divide instructions { saturated operation instructions { 32-bit shift instruction: 1 clock { load/store instruction with long/short format { four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 note this value may change after evaluation. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 46 3.2 cpu register set the cpu registers of the v850es/kf1+ can be classified into two categories: a general-purpose program register set and a dedicated system register set. all the registers have 32-bit width. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 47 3.2.1 program register set the program register set includes general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. all of these registers c an be used as a data variable or address variable. however, r0 and r30 are implicitly us ed by instructions and care must be ex ercised when using these registers. r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer when performing memory access with the sld and sst instructions. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. t herefore, before using these registers, their contents mu st be saved so that they are not lost, and they must be restor ed to the registers after the registers have been used. there are cases when r2 is used by the real-time os. if r2 is not used by the real-time os, r2 can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved regist er working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os to be used) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (area for placing program code) r6 to r29 address/data variable register r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution (2) program counter (pc) this register holds the address of the in struction under execution. the lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occu rs from bit 25 to bit 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address under execution 0 after reset 00000000h chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 48 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. read from and write to system regist ers are performed by setting the system register numbers shown below with the system register load/st ore instructions (ldsr, stsr instructions). table 3-2. system register numbers operand specification enabled system register no. system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 yes yes 1 interrupt status saving register (eipsw) note 1 yes yes 2 nmi status saving register (fepc) note 1 yes yes 3 nmi status saving register (fepsw) note 1 yes yes 4 interrupt source register (ecr) no yes 5 program status word (psw) yes yes 6 to 15 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no 16 callt execution status saving register (ctpc) yes yes 17 callt execution status saving register (ctpsw) yes yes 18 exception/debug trap status saving register (dbpc) yes note 2 yes 19 exception/debug trap status saving register (dbpsw) yes note 2 yes 20 callt base pointer (ctbp) yes yes 21 to 31 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no notes 1. since only one set of these registers is available, the contents of this register must be saved by the program when multiple interrupt servicing is enabled. 2. can be accessed only during the period from the dbtrap instruction to the dbret instruction. caution even if bit 0 of eipc, fepc, or ctpc is set (1) by the ldsr instruction, bit 0 is ignored during return with the reti instruction following interrupt servicing (because bit 0 of pc is fixed to 0). when setting a value to eipc, fepc, and ctpc, set an even number (bit 0 = 0). chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 49 (1) interrupt status saving registers (eipc, eipsw) there are two interrupt status sa ving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (pc) are saved to eipc and the contents of the program status word (psw) are saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), t he contents are saved to the nmi status saving registers (fepc, fepsw)). the address of the next instruction fo llowing the instruction executed when a software exception or maskable interrupt occurs is saved to eipc, e xcept for some instructions (refer to 19.9 periods in which interrupts are not acknowledged by cpu ). the current psw contents are saved to eipsw. since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved (fixed to 0) for future function expansion. when the reti instruction is execut ed, the values in eipc and eipsw are restored to the pc and psw, respectively. 31 0 eipc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 50 (2) nmi status saving registers (fepc, fepsw) there are two nmi status saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), the contents of the program co unter (pc) are saved to fepc and the contents of the program status word (psw) are saved to fepsw. the address of the next instruction fo llowing the instruction executed when a non-maskable interrupt occurs is saved to fepc, except fo r some instructions. the current psw contents are saved to fepsw. since there is only one set of nmi stat us saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is performed. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served (fixed to 0) for future function expansion. 31 0 fepc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (3) interrupt source register (ecr) upon occurrence of an interrupt or an exception, the inte rrupt source register (ecr) holds the source of an interrupt or an exception. the value held by ecr is the exception code c oded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 51 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the program status (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruct ion, the new contents become valid immediately following completion of ldsr instruction execution. interrupt request acknowledgment is held pending while a write to the psw is being executed by the ldsr instruction. bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servici ng is in progress. this flag is set to 1 when an nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in prog ress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt r equest acknowledgment is enabled. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do no t become saturated. this flag is neither set nor cleared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow occu rred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2 ov note indicates whether overflow o ccurred during an operation. 0: no overflow occurred 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0. remark note is explained on the following page. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 52 (2/2) note during saturated operation, the saturated operation results are dete rmined by the contents of the ov flag and s flag. the sat flag is set (to 1) only when the ov flag is set (to 1) during saturated operation. flag status operation result status sat ov s saturated operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation 0 1 actual operation result (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execut ion status saving registers, ctpc and ctpsw. when the callt instruction is execut ed, the contents of the program count er (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instructi on after the callt instruction. the current psw contents are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are re served (fixed to 0) for future function expansion. 31 0 ctpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 53 (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/de bug trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, the contents of the program counter (pc) are saved to dbpc, and the program status word (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instructi on after the instruction executed when an exception trap or debug trap occurs. the current psw contents are saved to dbpsw. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are re served (fixed to 0) for future function expansion. 31 0 dbpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 0 ctbp (base address) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 54 3.3 operating modes the v850es/kf1+ has the following operating modes. (1) normal operating mode after the system has been released from the reset state, t he pins related to the bus in terface are set to the port mode, execution branches to the reset entry address of the internal rom, and instruction processing is started. (2) flash memory programming mode this mode is valid only in flash memory versions ( pd70f3306, 70f3306y, 70f3308, and 70f3308y). when this mode is specified, the internal flash me mory can be programmed by using a flash programmer. (a) specifying operating mode the operating mode is specified acco rding to the status (input leve l) of the flmd0 and flmd1 pins. in the normal operating mode, input a low level to the flmd0 pin during the reset period. a high level is input to the flmd0 pin by the flash programmer in the flash memory programming mode if a flash programmer is connected. in the self-programming mode, input a high level to this pin from an external circuit. fix the specification of these pins in the application system and do not change the setting of these pins during operation. flmd0 flmd1 operating mode l normal operating mode h l flash memory programming mode h h setting prohibited remark h: high level l: low level : don?t care chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 55 3.4 address space 3.4.1 cpu address space up to 64 kb + 2 mb of external memory area in a linear address space (program space) of up to 64 mb, internal rom area, and internal ram area are supported for inst ruction address addressing. during operand addressing (data access), up to 4 gb of linear address space (data spac e) is supported. however, the 4 gb address space is viewed as 64 images of a 64 mb physical address space. in other words, the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. address space image program space internal ram area use-prohibited area use-prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 on-chip peripheral i/o area internal ram area use-prohibited area external memory area internal rom area (external memory area) 64 kb + 2 mb 4 gb 64 mb ? ? ? 64 mb chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 56 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the program counter (p c), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calc ulation, the higher 6 bits ignore this and remain 0. therefore, the lower-limit address of the program space, 0000 0000h, and the upper-limit address, 03ffffffh, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution no instructions can be fetched from the 4 kb area of 03fff000h to 03ffffffh because this area is an on-chip peripheral i/o area. the refore, do not execute any branch operation instructions in which the destination addres s will reside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit addre ss of the data space, address 0000 0000h, and the upper-limit address, ffffffffh, are contiguous addresses, and the data space is wrapped around at t he boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction (?) direction chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 57 3.4.3 memory map the v850es/kf1+ has reserved areas as shown below. figure 3-2. data memory map (physical addresses) 3ffffffh 3fec000h 3febfffh 0210000h 020ffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 3fff000h 3ffefffh 3fff000h 3ffefffh 3ffffffh 0000000h 3fec000h (80 kb) use-prohibited area internal rom area note (1 mb) external memory area (64 kb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use-prohibited area external memory area (64 kb) (2 mb) cs0 cs1 use-prohibited area 0110000h 010ffffh note fetch access and read access to addresses 0000000h to 00fffffh is performed for the internal rom area, but in the case of data write access, it is performed for an external memory area. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 58 figure 3-3. program memory map 03ff0000h 03feffffh 03fff000h 03ffefffh 03ffffffh 00210000h 0020ffffh 00100000h 000fffffh 00110000h 0010ffffh 00000000h internal ram area (60 kb) use-prohibited area (program fetch disabled area) use-prohibited area (program fetch disabled area) external memory area (64 kb) use-prohibited area (program fetch disabled area) external memory area (64 kb) internal rom area (1 mb) cs0 cs1 00200000h 001fffffh chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 59 3.4.4 areas (1) internal rom area an area of 1 mb from 0000000h to 00fffffh is reserved for the internal rom area. (a) internal rom (256 kb) a 256 kb area from 0000000h to 003ffffh is provided in the fo llowing products. addresses 0040000h to 00fffffh are an access-prohibited area. ? pd703308, 703308y, 70f3308, 70f3308y figure 3-4. internal rom area (256 kb) access-prohibited area internal rom area (256 kb) 0040000h 00fffffh 003ffffh 0000000h (b) internal rom (128 kb) a 128 kb area from 0000000h to 001ffffh is provided in the fo llowing products. addresses 0020000h to 00fffffh are an access-prohibited area. ? pd70f3306, 70f3306y figure 3-5. internal rom area (128 kb) 00fffffh 0020000h 001ffffh 0000000h access-prohibited area internal rom area (128 kb) chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 60 (2) internal ram area an area of 60 kb maximum from 3ff0000h to 3ffef ffh is reserved for the internal ram area. (a) internal ram (12 kb) a 12 kb area from 3ffc000h to 3ffefffh is provided as physical internal ram in the following products. addresses 3ff0000h to 3ffbfffh ar e an access-prohibited area. ? pd703308, 703308y, 70f3308, 70f3308y figure 3-6. internal ram area (12 kb) internal ram area (12 kb) access-prohibited area physical address space logical address space 3ffc000h 3ffefffh 3ffbfffh 3ff0000h fffc000h fffefffh fffbfffh fff0000h chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 61 (b) internal ram (6 kb) a 6 kb area from 3ffd800h to 3ffefffh is provided as physical internal ram in the following products. addresses 3ff0000h to 3ffd7ffh are an access-prohibited area. ? pd70f3306, 70f3306y figure 3-7. internal ram area (6 kb) internal ram area (6 kb) access-prohibited area 3ffefffh 3ffd800h 3ffd7ffh 3ff0000h fffefffh fffd800h fffd7ffh fff0000h physical address space logical address space chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 62 (3) on-chip peripheral i/o area a 4 kb area from 3fff000h to 3ffffffh is rese rved as the on-chip peripheral i/o area. figure 3-8. on-chip peripheral i/o area 3ffffffh 3fff000h on-chip peripheral i/o area (4 kb) fffffffh ffff000h physical address space logical address space peripheral i/o registers assigned with functions such as on-chip peripheral i/o operation mode specification and state monitoring are mapped to the on-chip peripheral i/o area. program fetches are not allowed in this area. cautions 1. if word access of a register is atte mpted, halfword access to th e word area is performed twice, first for the lower bits , then for the higher bits, ignoring the lower 2 address bits. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the access is a read operation. if a write access is performed, only the data in the lower 8 bits is written to the register. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. (4) external memory area 128 kb (0100000h to 010ffffh, 0200000h to 020ffffh) are provided as the external memory area. for details, refer to chapter 5 bus control function . chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 63 3.4.5 recommended use of address space the architecture of the v 850es/kf1+ requires that a r egister that serves as a pointer be secured for address generation when operand data in t he data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. be cause the number of general-pur pose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose regist ers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, theref ore, a 64 mb space of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the progr am space, access the following addresses. ram size access address 6 kb 3ffd800h to 3ffefffh 12 kb 3ffc000h to 3ffefffh (2) data space with the v850es/kf1+, it seems that there are sixty-four 64 mb physi cal address spaces on the 4 gb cpu address space. therefore, the least si gnificant bit (bit 25) of a 26-bit ad dress is sign-extended to 32 bits and allocated as an address. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 64 (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically elimin ates the need for registers dedicated to pointers. example : pd703308, 703308y 32 kb 4 kb 12 kb 16 kb internal rom area on-chip peripheral i/o area access-prohibited area (r = ) 0003ffffh 00007fffh 00000000h fffff000h ffffefffh ffff8000h internal ram area ffffc000h ffffbfffh chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 65 figure 3-9. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram on-chip peripheral i/o note internal rom internal rom program space 64 mb xfffffffh xffff000h xfffefffh xfffc000h xfffbfffh xffec000h xffebfffh ffffffffh fffff000h ffffefffh fffec000h fffebfffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffc000h 03ffbfffh 03fec000h 03febfffh 00210000h 0020ffffh 00040000h 0003ffffh 00100000h 000fffffh 00000000h external memory use prohibited external memory use prohibited 00200000h 001fffffh 00110000h 0010ffffh x0210000h x020ffffh x0100000h x00fffffh x0000000h x0200000h x01fffffh x0110000h x000ffffh note access to this area is prohibited. to access the on-chip peripheral i/o in th is area, specify addresses ffff000h to fffffffh. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd703308 and 703308y. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 66 3.4.6 peripheral i/o registers (1/8) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff004h port dl register pdl r/w chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 67 (2/8) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff12ah interrupt control register tm5ic1 r/w 47h fffff12ch interrupt control register csi0ic0 r/w 47h fffff12eh interrupt control register csi0ic1 r/w 47h fffff130h interrupt control register sreic0 r/w 47h fffff132h interrupt control register sric0 r/w 47h fffff134h interrupt control register stic0 r/w 47h fffff136h interrupt control register sreic1 r/w 47h fffff138h interrupt control register sric1 r/w 47h fffff13ah interrupt control register stic1 r/w 47h fffff13ch interrupt control register tmhic0 r/w 47h fffff13eh interrupt control register tmhic1 r/w 47h fffff140h interrupt control register csiaic0 r/w 47h fffff142h interrupt control register iicic0 note 1 r/w 47h fffff144h interrupt control register adic r/w 47h fffff146h interrupt control register kric r/w 47h fffff148h interrupt control register wtiic r/w 47h fffff14ah interrupt control register wtic r/w 47h fffff14ch interrupt control register brgic r/w 47h fffff170h interrupt control register lviic r/w 47h fffff172h interrupt control register pic7 r/w 47h fffff174h interrupt control register tp0ovic r/w 47h fffff176h interrupt control register tp0ccic0 r/w 47h fffff178h interrupt control register tp0ccic1 r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w 00h fffff200h a/d converter mode register adm r/w 00h fffff201h analog input channel specification register ads r/w 00h fffff202h power fail comparison mode register pfm r/w 00h fffff203h power fail comparison threshold register pft r/w 00h fffff204h a/d conversion result register adcr r undefined fffff205h a/d conversion result register h adcrh r undefined fffff300h key return mode register krm r/w 00h fffff308h selector operation control register 0 selcnt0 r/w 00h fffff30ah selector operation control register 1 selcnt1 r/w 00h fffff318h digital noise elimination control register nfc r/w 00h fffff400h port 0 register p0 r/w 00h note 2 fffff406h port 3 register p3 r/w 0000h note 2 fffff406h port 3 register l p3l r/w 00h note 2 fffff407h port 3 register h p3h r/w 00h note 2 fffff408h port 4 register p4 r/w 00h note 2 notes 1. only in the pd703308y, 70f3306y, 70f3308y 2. the output latch is 00h or 0000h. when input, the pin status is read. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 68 (3/8) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff40ah port 5 register p5 r/w 00h note fffff40eh port 7 register p7 r undefined fffff412h port 9 register p9 r/w 0000h note fffff412h port 9 register l p9l r/w 00h note fffff413h port 9 register h p9h r/w 00h note fffff420h port 0 mode register pm0 r/w feh fffff426h port 3 mode register pm3 r/w ffffh fffff426h port 3 mode register l pm3l r/w ffh fffff427h port 3 mode register h pm3h r/w ffh fffff428h port 4 mode register pm4 r/w ffh fffff42ah port 5 mode register pm5 r/w ffh fffff432h port 9 mode register pm9 r/w ffffh fffff432h port 9 mode register l pm9l r/w ffh fffff433h port 9 mode register h pm9h r/w ffh fffff440h port 0 mode control register pmc0 r/w 00h fffff446h port 3 mode control register pmc3 r/w 0000h fffff446h port 3 mode control register l pmc3l r/w 00h fffff447h port 3 mode control register h pmc3h r/w 00h fffff448h port 4 mode control register pmc4 r/w 00h fffff44ah port 5 mode control register pmc5 r/w 00h fffff452h port 9 mode control register pmc9 r/w 0000h fffff452h port 9 mode control register l pmc9l r/w 00h fffff453h port 9 mode control register h pmc9h r/w 00h fffff466h port 3 function control register pfc3 r/w 00h fffff46ah port 5 function control register pfc5 r/w 00h fffff472h port 9 function control register pfc9 r/w 0000h fffff472h port 9 function control register l pfc9l r/w 00h fffff473h port 9 function control register h pfc9h r/w 00h fffff484h data wait control register 0 dwc0 r/w 7777h fffff488h address wait control register awc r/w ffffh fffff48ah bus cycle control register bcc r/w aaaah fffff580h 8-bit timer h mode register 0 tmhmd0 r/w 00h fffff581h 8-bit timer h carrier control register 0 tmcyc0 r/w 00h fffff582h 8-bit timer h compare register 00 cmp00 r/w 00h fffff583h 8-bit timer h compare register 01 cmp01 r/w 00h fffff590h 8-bit timer h mode register 1 tmhmd1 r/w 00h fffff591h 8-bit timer h carrier control register 1 tmcyc1 r/w 00h fffff592h 8-bit timer h compare register 10 cmp10 r/w 00h fffff593h 8-bit timer h compare register 11 cmp11 r/w 00h fffff5a0h tmp0 control register 0 tp0ctl0 r/w 00h fffff5a1h tmp0 control register 1 tp0ctl1 r/w 00h fffff5a2h tmp0 i/o control register 0 tp0ioc0 r/w 00h note the output latch is 00h or 0000h. when input, the pin status is read. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 69 (4/8) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff5a3h tmp0 i/o control register 1 tp0ioc1 r/w 00h fffff5a4h tmp0 i/o control register 2 tp0ioc2 r/w 00h fffff5a5h tmp0 option register 0 tp0opt0 r/w 00h fffff5a6h tmp0 capture/compare register 0 tp0ccr0 r/w 0000h fffff5a8h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff5aah tmp0 counter read buffer register tp0cnt r 0000h fffff5c0h 16-bit timer counter 5 tm5 r 0000h fffff5c0h 8-bit timer counter 50 tm50 r 00h fffff5c1h 8-bit timer counter 51 tm51 r 00h fffff5c2h 16-bit timer compare register 5 cr5 r/w 0000h fffff5c2h 8-bit timer compare register 50 cr50 r/w 00h fffff5c3h 8-bit timer compare register 51 cr51 r/w 00h fffff5c4h timer clock selection register 5 tcl5 r/w 0000h fffff5c4h timer clock selection register 50 tcl50 r/w 00h fffff5c5h timer clock selection register 51 tcl51 r/w 00h fffff5c6h 16-bit timer mode control register 5 tmc5 r/w 0000h fffff5c6h 8-bit timer mode control register 50 tmc50 r/w 00h fffff5c7h 8-bit timer mode control register 51 tmc51 r/w 00h fffff600h 16-bit timer counter 00 tm00 r 0000h fffff602h 16-bit timer capture/compare register 000 cr000 r/w 0000h fffff604h 16-bit timer capture/compare register 001 cr001 r/w 0000h fffff606h 16-bit timer mode control register 00 tmc00 r/w 00h fffff607h prescaler mode register 00 prm00 r/w 00h fffff608h capture/compare control register 00 crc00 r/w 00h fffff609h 16-bit timer output control register 00 toc00 r/w 00h fffff610h 16-bit timer counter 01 tm01 r 0000h fffff612h 16-bit timer capture/compare register 010 cr010 r/w 0000h fffff614h 16-bit timer capture/compare register 011 cr011 r/w 0000h fffff616h 16-bit timer mode control register 01 tmc01 r/w 00h fffff617h prescaler mode register 01 prm01 r/w 00h fffff618h capture/compare control register 01 crc01 r/w 00h fffff619h 16-bit timer output control register 01 toc01 r/w 00h fffff680h watch timer operation mode register wtm r/w 00h fffff6c0h oscillation stabilization time selection register osts r/w note fffff6c1h watchdog timer clock sele ction register wdcs r/w 00h fffff6c2h watchdog timer mode register 1 wdtm1 r/w 00h fffff6d0h watchdog timer mode register 2 wdtm2 r/w 67h fffff6d1h watchdog timer enable register wdte r/w 9ah fffff6e0h real-time output buffer register l0 rtbl0 r/w 00h fffff6e2h real-time output buffer register h0 rtbh0 r/w 00h fffff6e4h real-time output port mode register 0 rtpm0 r/w 00h note the value can be set to 00h or 01h by the option byte or a mask option setting. for details, refer to chapter 28 mask option/option byte. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 70 (5/8) operable bit unit address function register name symbol r/w 1 8 16 32 after reset fffff6e5h real-time output port control register 0 rtpc0 r/w chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 71 (6/8) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffa17h baud rate generator control register 1 brgc1 r/w ffh fffffb00h tip00 noise elimination control register p0nfc r/w 00h fffffb04h tip01 noise elimination control register p1nfc r/w 00h fffffc00h external interrupt falling edge specification register 0 intf0 r/w 00h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 00h fffffc13h external interrupt falling edge specification register 9h intf9h r/w 00h fffffc20h external interrupt rising edge specification register 0 intr0 r/w 00h fffffc26h external interrupt rising edge specification register 3 intr3 r/w 00h fffffc33h external interrupt rising edge specification register 9h intr9h r/w 00h fffffc40h pull-up resistor option register 0 pu0 r/w 00h fffffc46h pull-up resistor option register 3 pu3 r/w 00h fffffc48h pull-up resistor option register 4 pu4 r/w 00h fffffc4ah pull-up resistor option register 5 pu5 r/w 00h fffffc52h pull-up resistor option register 9 pu9 r/w 0000h fffffc52h pull-up resistor option register 9l pu9l r/w 00h fffffc53h pull-up resistor option register 9h pu9h r/w 00h fffffc67h port 3 function register h pf3h r/w 00h fffffc68h port 4 function register pf4 r/w 00h fffffc6ah port 5 function register pf5 r/w 00h fffffc73h port 9 function register h pf9h r/w 00h fffffd00h clocked serial interf ace mode register 00 csim00 r/w 00h fffffd01h clocked serial interface clock selection register 0 csic0 r/w 00h fffffd02h clocked serial interface re ceive buffer register 0 sirb0 r 0000h fffffd02h clocked serial interface receive buffer register 0l sirb0l r 00h fffffd04h clocked serial interface tran smit buffer register 0 sotb0 r/w 0000h fffffd04h clocked serial interface tr ansmit buffer register 0l sotb0l r/w 00h fffffd06h clocked serial interface read-onl y receive buffer register 0 sirbe0 r 0000h fffffd06h clocked serial interface read- only receive buffer register 0l sirbe0l r 00h fffffd08h clocked serial interface initial transmit buffer register 0 sotbf0 r/w 0000h fffffd08h clocked serial interface initia l transmit buffer register 0l sotbf0l r/w 00h fffffd0ah serial i/o shift register 0 sio00 r/w 00h fffffd0ah serial i/o shift register 0l sio00l r/w 0000h fffffd10h clocked serial interf ace mode register 01 csim01 r/w 00h fffffd11h clocked serial interface clock selection register 1 csic1 r/w 00h fffffd12h clocked serial interface re ceive buffer register 1 sirb1 r 0000h fffffd12h clocked serial interface receive buffer register 1l sirb1l r 00h fffffd14h clocked serial interface tran smit buffer register 1 sotb1 r/w 0000h fffffd14h clocked serial interface tr ansmit buffer register 1l sotb1l r/w 00h fffffd16h clocked serial interface read-onl y receive buffer register 1 sirbe1 r 0000h fffffd16h clocked serial interface read- only receive buffer register 1l sirbe1l r 00h fffffd18h clocked serial interface initial transmit buffer register 1 sotbf1 r/w 0000h fffffd18h clocked serial interface initia l transmit buffer register 1l sotbf1l r/w 00h chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 72 (7/8) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffd1ah serial i/o shift register 1 sio01 r/w 00h fffffd1ah serial i/o shift register 1l sio01l r/w 0000h fffffd40h serial operation mode specification register 0 csima0 r/w 00h fffffd41h serial status register 0 csis0 r/w 00h fffffd42h serial trigger register 0 csit0 r/w 00h fffffd43h divisor selection register 0 brgca0 r/w 03h fffffd44h automatic data transfer address point specification register 0 adtp0 r/w 00h fffffd45h automatic data transfer interval specification register 0 adti0 r/w 00h fffffd46h serial i/o shift register a0 sioa0 r/w 00h fffffd47h automatic data transfer address count register 0 adtc0 r 00h fffffd80h iic shift register 0 iic0 note r/w 00h fffffd82h iic control register 0 iicc0 note r/w 00h fffffd83h slave address register 0 sva0 note r/w 00h fffffd84h iic clock selection register 0 iiccl0 note r/w 00h fffffd85h iic function expansion register 0 iicx0 note r/w 00h fffffd86h iic status register 0 iics0 note r 00h fffffd8ah iic flag register 0 iicf0 note r/w 00h fffffe00h csia0 buffer ram 0 csia0b0 r/w undefined fffffe00h csia0 buffer ram 0l csia0b0l r/w undefined fffffe01h csia0 buffer ram 0h csia0b0h r/w undefined fffffe02h csia0 buffer ram 1 csia0b1 r/w undefined fffffe02h csia0 buffer ram 1l csia0b1l r/w undefined fffffe03h csia0 buffer ram 1h csia0b1h r/w undefined fffffe04h csia0 buffer ram 2 csia0b2 r/w undefined fffffe04h csia0 buffer ram 2l csia0b2l r/w undefined fffffe05h csia0 buffer ram 2h csia0b2h r/w undefined fffffe06h csia0 buffer ram 3 csia0b3 r/w undefined fffffe06h csia0 buffer ram 3l csia0b3l r/w undefined fffffe07h csia0 buffer ram 3h csia0b3h r/w undefined fffffe08h csia0 buffer ram 4 csia0b4 r/w undefined fffffe08h csia0 buffer ram 4l csia0b4l r/w undefined fffffe09h csia0 buffer ram 4h csia0b4h r/w undefined fffffe0ah csia0 buffer ram 5 csia0b5 r/w undefined fffffe0ah csia0 buffer ram 5l csia0b5l r/w undefined fffffe0bh csia0 buffer ram 5h csia0b5h r/w undefined fffffe0ch csia0 buffer ram 6 csia0b6 r/w undefined fffffe0ch csia0 buffer ram 6l csia0b6l r/w undefined fffffe0dh csia0 buffer ram 6h csia0b6h r/w undefined fffffe0eh csia0 buffer ram 7 csia0b7 r/w undefined fffffe0eh csia0 buffer ram 7l csia0b7l r/w undefined fffffe0fh csia0 buffer ram 7h csia0b7h r/w undefined note only in the pd703308y, 70f3306y, 70f3308y chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 73 (8/8) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffe10h csia0 buffer ram 8 csia0b8 r/w undefined fffffe10h csia0 buffer ram 8l csia0b8l r/w undefined fffffe11h csia0 buffer ram 8h csia0b8h r/w undefined fffffe12h csia0 buffer ram 9 csia0b9 r/w undefined fffffe12h csia0 buffer ram 9l csia0b9l r/w undefined fffffe13h csia0 buffer ram 9h csia0b9h r/w undefined fffffe14h csia0 buffer ram a csia0ba r/w undefined fffffe14h csia0 buffer ram al csia0bal r/w undefined fffffe15h csia0 buffer ram ah csia0bah r/w undefined fffffe16h csia0 buffer ram b csia0bb r/w undefined fffffe16h csia0 buffer ram bl csia0bbl r/w undefined fffffe17h csia0 buffer ram bh csia0bbh r/w undefined fffffe18h csia0 buffer ram c csia0bc r/w undefined fffffe18h csia0 buffer ram cl csia0bcl r/w undefined fffffe19h csia0 buffer ram ch csia0bch r/w undefined fffffe1ah csia0 buffer ram d csia0bd r/w undefined fffffe1ah csia0 buffer ram dl csia0bdl r/w undefined fffffe1bh csia0 buffer ram dh csia0bdh r/w undefined fffffe1ch csia0 buffer ram e csia0be r/w undefined fffffe1ch csia0 buffer ram el csia0bel r/w undefined fffffe1dh csia0 buffer ram eh csia0beh r/w undefined fffffe1eh csia0 buffer ram f csia0bf r/w undefined fffffe1eh csia0 buffer ram fl csia0bfl r/w undefined fffffe1fh csia0 buffer ram fh csia0bfh r/w undefined ffffff44h pull-up resistor option register dl pudl r/w 0000h ffffff44h pull-up resistor option register dll pudll r/w 00h ffffff45h pull-up resistor option register dlh pudlh r/w 00h ffffff48h pull-up resistor option register cs pucs r/w 00h ffffff4ah pull-up resistor option register ct puct r/w 00h ffffff4ch pull-up resistor option register cm pucm r/w 00h chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 74 3.4.7 special registers special registers are registers that prevent invalid da ta from being written when an inadvertent program loop occurs. the v850es/kf1+ has the following six special registers. ? power save control register (psc) ? processor clock control register (pcc) ? watchdog timer mode register (wdtm1) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) moreover, there is also the prcmd r egister, which is a protection register for write operations to the special registers that prevents the application system from unexpectedly stopping due to an inadvertent program loop. write access to the special registers is performed with a specia l sequence and illegal store oper ations are notified to the sys register. (1) setting data to special registers setting data to a special register is done in the following sequence. <1> prepare the data to be set to the specia l register in a general-purpose register. <2> write the data prepared in st ep <1> to the prcmd register. <3> write the setting data to the special regi ster (using following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <4> to <8> insert nop inst ructions (5 instructions) note . note when switching to the idle mode or the stop m ode (psc.stp bit = 1), 5 nop instructions must be inserted immediately after switching is performed. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 75 [description example] when using psc register (standby mode setting) st.b r11, psmr[r0] ; psmr register setting (idle, stop mode setting) <1> mov 0x02, r10 <2> st.b r10, prcmd[r0] ; prcmd register write <3> st.b r10, psc[r0] ; psc register setting <4> nop note ; dummy instruction <5> nop note ; dummy instruction <6> nop note ; dummy instruction <7> nop note ; dummy instruction <8> nop note ; dummy instruction (next instruction) no special sequence is required to read special registers. note when switching to the idle mode or the stop mode (psc.stp bit = 1), 5 nop instructions must be inserted immediately after switching is performed. cautions 1. interrupts are not acknowledged for the store instruction for the prcmd register. this is because continuous execution of store instructi ons by the program in steps <2> and <3> above is assumed. if another instruction is placed between step <2> and <3>, the above sequence may not be realized when an interrupt is acknowle dged for that instruction, which may cause malfunction. 2. the data written to the prcmd register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <3>) when writing to the prcmd register (step <2>). the same applies to when using a general- purpose register for addressing. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 76 (2) command register (prcmd) the prcmd register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs. only the first write operat ion to the special register following the execution of a previously executed writ e operation to the prcmd register, is valid. as a result, register values can be overwritten onl y using a preset sequence, preventing invalid write operations. this register can only be written in 8-bit units (if it is read, an undefined value is returned). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 77 (3) system status register (sys) this register is allocated with status flags showing the operat ing state of the entire system. this register can be read or writt en in 8-bit or 1-bit units. 0 protection error has not occurred protection error has occurred prerr 0 1 detection of protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the operation conditions of the prerr flag are described below. (a) set conditions (prerr = 1) (i) when a write operation to the s pecial register takes place without write operation being performed to the prcmd register (when step <3> is performed without performing step <2> as described in 3.4.7 (1) setting data to special registers ). (ii) when a write operation (including bit manipulation instruction) to an on-chip peripheral i/o register other than a special register is performed follo wing write to the prcmd register (when <3> in 3.4.7 (1) setting data to special registers is not a special register). remark regarding the special registers other than the wdtm register (pcc and psc registers), even if on-chip peripheral i/o register read (except bit ma nipulation instruction) (internal ram access, etc.) is performed in between wr ite to the prcmd register and wr ite to a special register, the prerr flag is not set and setting data can be written to the special register. (b) clear conditions (prerr = 0) (i) when 0 is written to the prerr flag (ii) when system reset is performed cautions 1. if 0 is written to the prerr bit of the sys register that is not a special register immediately following write to the prcmd re gister, the prerr bi t becomes 0 (write priority). 2. if data is written to the prcmd register that is not a special register immediately following write to the prcmd regist er, the prerr bit becomes 1. chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 78 3.4.8 cautions (1) wait when accessing register be sure to set the following register before using the v850es/kf1+. ? chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 79 peripheral function register name access k wdtm1 write 1 to 5 watchdog timer 1 (wdt1) chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 80 caution when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wait occurs using an acc ess method that causes a wait . if a wait occurs, it can only be released by a reset. remark in the calculation for the number of waits: f cpu : cpu clock frequency m: set value of bits 2 to 0 of the vswc register f clk : internal system clock when f clk < 16.6 mhz: m = 0 when f clk 16.6 mhz: m = 1 the digits below the decimal poi nt are truncated if less than (1/ f cpu )/(2 + m) or rounded up if larger than (1/ f cpu )/(2 + m) when multiplied by (1/ f cpu ). chapter 3 cpu functions preliminary user?s manual u16895ej1v0ud 81 (2) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the dec ode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of t he instruction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 preliminary user?s manual u16895ej1v0ud 82 chapter 4 port functions 4.1 features { input-only ports: 8 pins { i/o ports: 59 pins ? ? { input/output can be specified in 1-bit units 4.2 basic port configuration the v850es/kf1+ incorporates a total of 67 i/o port pins c onsisting of ports 0, 3 to 5, 7, 9, cm, cs, ct, and dl (including 8 input-only port pins). the port configuration is shown below. p00 p06 port 0 p90 p91 port 9 pcm0 pcm3 port cm pcs0 pcs1 port cs pct0 pct1 pct4 pct6 port ct pdl0 pdl15 port dl p38 p39 port 3 p40 p42 port 4 p50 p55 port 5 p70 p77 port 7 p30 p35 p96 p99 p913 p915 table 4-1. pin i/o buffer po wer supplies of v850es/kf1+ power supply corresponding pins av ref0 port 7 ev dd reset, ports 0, 3 to 5, 9, cm, cs, ct, dl chapter 4 port functions preliminary user?s manual u16895ej1v0ud 83 4.3 port configuration table 4-2. port configuration item configuration control registers port n register (pn: n = 0, 3 to 5, 7, 9, cm, cs, ct, dl) port n mode register (pmn: n = 0, 3 to 5, 9, cm, cs, ct, dl) port n mode control register (pmcn: n = 0, 3 to 5, 9, cm, cs, ct, dl) port n function control register (pfcn: n = 3, 5, 9) port n function register (pfn: n = 3 to 5, 9) port 3 function control expansion register (pfce3) pull-up resistor option register (pun: n = 0, 3 to 5, 9, cm, cs, ct, dl) ports input only: 8 i/o: 59 pull-up resistors software control: 48 (1) port n register (pn) data i/o with external devices is performed by writing to and reading from the pn regist er. the pn register is configured of a port latch that re tains the output data and a circ uit that reads the pin status. each bit of the pn register corresponds to one pin of port n and can be read or written in 1-bit units. pn7 0 is output 1 is output pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h note (output latch) r/w note input-only port pins are undefined. writing to and reading from the pn register is executed as follows independent of the se tting of the pmcn register. table 4-3. reading to/writing from pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm bit = 0) write to the output latch note . in the port mode (pmcnm bit = 0), the contents of the output latch are output from the pin. the value of the output latch is read. input mode (pmnm bit = 1) write to the output latch. the status of the pin is not affected note . the pin status is read. note the value written to the output latch is retained until a value is next written to the output latch. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 84 (2) port n mode register (pmn) pmn specifies the input m ode/output mode of the port. each bit of the pmn register corresponds to one pin of port n and can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of i/o mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) pmcn specifies the port mode/alternate function. each bit of the pmcn register corresponds to one pin of port n and can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w (4) port n function control register (pfcn) pfcn is a register that specifies the alternate function to be us ed when one pin has two or more alternate functions. each bit of the pfcn register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function chapter 4 port functions preliminary user?s manual u16895ej1v0ud 85 (5) port n function control expansion register (pfcen) pfcen is a register that specifies t he alternate function to be used when one pin has three or more alternate functions. each bit of the pfcen register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 (6) port n function register (pfn) pfn is a register that specifies normal output/n-ch open-drain output. each bit of the pfn register corresponds to one pin of port n and can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit is valid only when the pmn.pmnm bit is 0 (output mode) regardl ess of the setting of the pmcn register. when the pmnm bit is 1 (input mode) , the set value in the pfn register is invalid. example <1> when the value of t he pfn register is valid pfnm bit = 1 ? n-ch open-drain output is specified. pmnm bit = 0 ? output mode is specified. pmcnm bit = 0 or 1 <2> when the value of the pfn register is invalid pfnm bit = 0 ? n-ch open-drain output is specified. pmnm bit = 1 ? input mode is specified. pmcnm bit = 0 or 1 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 86 (7) pull-up resistor option register (pun) pun is a register that specifies the c onnection of an on-chip pull-up resistor. each bit of the pun register corresponds to one pin of port n and can be specified in 1-bit units. pun7 pun6 pun5 pun4 pun3 pun2 pun1 pun0 pun after reset: 00h r/w not connected connected punm 0 1 control of on-chip pull-up resistor connection chapter 4 port functions preliminary user?s manual u16895ej1v0ud 87 (8) port settings set the ports as follows. figure 4-1. register settings and pin functions pmcn register output mode input mode pmn register ? 0 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark switch to the alternate functi on using the following procedure. <1> set the pfcn and pfcen registers. <2> set the pmcn register. <3> set the intrn or intfn register (t o specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 88 4.3.1 port 0 port 0 is a 7-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 0 includes the following alternate functions. table 4-4. alternate-function pins of port 0 pin no. pin name alternate function i/o pull note 1 remark block type 3 p00 note 2 toh0 output d0-u 4 p01 toh1 output ? d0-u 5 p02 nmi input d1-suil 6 p03 intp0 input d1-suil 7 p04 intp1 input d1-suil 17 p05 intp2 input analog noise elimination d1-suil 18 p06 intp3 input yes analog/digital noise elimination d1-suil notes 1. software pull-up function 2. only the p00 pin outputs a low level after reset (other port pins are in input mode). therefore, the low-level output from the p00 pin after reset can be used as a dummy reset signal from the cpu. caution p02 to p06 have hysteresis characteristics when the alternate f unction is input, but not in the port mode. (1) port 0 register (p0) 0 0 is output 1 is output p0n 0 1 control of output data (in output mode) (n = 0 to 6) p0 p06 p05 p04 p03 p02 p01 p00 after reset: 00h (output latch) r/w address: fffff400h (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 control of i/o mode (n = 0 to 6) pm0 pm06 pm05 pm04 pm03 pm02 pm01 pm00 after reset: feh r/w address: fffff420h chapter 4 port functions preliminary user?s manual u16895ej1v0ud 89 (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode i/o port toh1 output pmc01 0 1 specification of p01 pin operation mode i/o port toh0 output pmc00 0 1 specification of p00 pin operation mode after reset: 00h r/w address: fffff440h (4) pull-up resistor option register 0 (pu0) 0 not connected connected pu0n 0 1 control of on-chip pull-up resistor connection (n = 0 to 6) pu0 pu06 pu05 pu04 pu03 pu02 pu01 pu00 after reset: 00h r/w address: fffffc40h chapter 4 port functions preliminary user?s manual u16895ej1v0ud 90 4.3.2 port 3 port 3 is an 8-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port 3 includes the following alternate functions. table 4-5. alternate-function pins of port 3 pin no. pin name alternate function i/o pull note 1 remark block type 22 p30 txd0 output d0-u 23 p31 rxd0/intp7 input d1-suihl 24 p32 asck0/adtrg/to01 i/o e10-sul 25 p33 ti000/to00/tip00/top00 i/o g1010-sul 26 p34 ti001/to00/tip01/top01 i/o g1010-sul 27 p35 ti010/to01 i/o yes ? e10-sul 28 p38 sda0 note 3 i/o d2-snmufh 29 p39 scl0 note 3 i/o no note 2 n-ch open-drain output d2-snmufh notes 1. software pull-up function 2. an on-chip pull-up resistor can be provided by a mask option (only in the pd703308, 703308y). 3. only in the pd703308y, 70f3306y, 70f3308y caution p31 to p35, p38, and p39 have hysteresis characteristics when th e alternate function is input, but not in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 91 (1) port 3 register (p3) 0 is output 1 is output p3n 0 1 control of output data (in output mode) (n = 0 to 5, 8, 9) p3 (p3h note ) after reset: 00h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h 0 0 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 p39 p38 8 9 10 11 12 13 14 15 (p3l) note when reading from or writing to bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p3h register. remark the p3 register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the p3 register are used as the p3h register and as the p3l register, re spectively, this register can be read or written in 8-bit or 1-bit units. (2) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 control of i/o mode (n = 0 to 5, 8, 9) 1 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 1 pm3 (pm3h note ) 1 1 1 1 1 pm39 pm38 8 9 10 11 12 13 14 15 (pm3l) note when reading from or writing to bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm3h register. remark the pm3 register can be read or written in 16-bit units. when the higher 8 bits and the lower 8 bits of the pm3 register are used as the pm3h register and as the pm3l register, respective ly, this register can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 92 (3) port 3 mode control register (pmc3) pmc3 (pmc3h note 1 ) i/o port scl0 i/o pmc39 0 1 specification of p39 pin operation mode i/o port sda0 i/o pmc38 0 1 specification of p38 pin operation mode i/o port ti010 input/to01 output pmc35 0 1 specification of p35 pin operation mode i/o port ti001 input/to00 output/tip01 input/top01 output pmc34 0 1 specification of p34 pin operation mode i/o port ti000 input/to00 output/tip00 input/top00 output pmc33 0 1 specification of p33 pin operation mode i/o port asck0 input/adtrg input/to01 output pmc32 0 1 specification of p32 pin operation mode i/o port rxd0 input/intp7 input note 3 pmc31 0 1 specification of p31 pin operation mode i/o port txd0 output pmc30 0 1 specification of p30 pin operation mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 00 00 00 pmc39 note 2 pmc38 note 2 8 9 10 11 12 13 14 15 (pmc3l) notes 1. when reading from or writing to bi ts 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc3h register. 2. valid only in the pd703308y, 70f3306y, 70f3308y. in all other products, set this bit to 0. 3. the intp7 and rxd0 pins are alternate-function pins. when using the pin as the rxd0 pin, disable edge detection of the alternate-function intp7 pin (clear the intf3.intf31 and intr3.intr31 bits to 0). when using the pin as the intp7 pin, stop t he uart0 receive operation (clear the asim0.rxe0 bit to 0). remark the pmc3 register can be read or written in 16-bit units. when the higher 8 bits and the lower 8 bits of the pmc3 register are used as the pmc3h register and as the pmc3l register, respectively, this register can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 93 (4) port 3 function register h (pf3h) 0 when used as normal port (n-ch open-drain output) when used as alternate-function (n-ch open-drain output) pf3n 0 1 specification of normal port/alternate function (n = 8, 9) pf3h 0 0 0 0 0 pf39 pf38 after reset: 00h r/w address: fffffc67h caution when using p38 and p39 as n-ch open-drai n-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p3n bit = 1 pf3n bit = 1 pmc3n bit = 1 (5) port 3 function control register (pfc3) pfc3 after reset: 00h r/w address: fffff466h 0 0 pfc35 pfc34 pfc33 pfc32 0 0 remark for details of specification of alternate-function pins, refer to 4.3.2 (7) specifying alternate-function pins of port 3 . (6) port 3 function contro l expansion register (pfce3) pfce3 after reset: 00h r/w address: fffff706h 0 0 0 pfce34 pfce33 0 0 0 remark for details of specification of alternate-function pins, refer to 4.3.2 (7) specifying alternate-function pins of port 3 . chapter 4 port functions preliminary user?s manual u16895ej1v0ud 94 (7) specifying alternate-function pins of port 3 pfc35 specification of alter nate-function pin of p35 pin 0 ti010 input 1 to01 output pfce34 pfc34 specification of alte rnate-function pin of p34 pin 0 0 ti001 input 0 1 to00 output 1 0 tip01 input 1 1 top01 output pfce33 pfc33 specification of alte rnate-function pin of p33 pin 0 0 ti000 input 0 1 to00 output 1 0 tip00 input 1 1 top00 output pfc32 specification of alter nate-function pin of p32 pin 0 asck0/adtrg note input 1 to01 output note the asck0 and adtrg pins are alternate-function pi ns. when using the pin as the asck0 pin, disable the trigger input of the alternate-f unction adtrg pin (clear the ads.trg bit to 0 or set the ads.adtmd bit to 1). when using the pin as the adtrg pin, do not set the uart0 operation clock to external input (set the cksr0.tps03 to cksr0.tps00 bits to other than 1011). (8) pull-up resistor option register 3 (pu3) 0 not connected connected pu3n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) pu3 0 pu35 pu34 pu33 pu32 pu31 pu30 after reset: 00h r/w address: fffffc46h caution an on-chip pull-up r esistor can be provided for p38 and p39 by a mask option (only in the pd703308, 703308y). chapter 4 port functions preliminary user?s manual u16895ej1v0ud 95 4.3.3 port 4 port 4 is a 3-bit i/o port for which i/o se ttings can be controll ed in 1-bit units. port 4 includes the following alternate functions. table 4-6. alternate-function pins of port 4 pin no. pin name alternate function i/o pull note remark block type 19 p40 si00 input ? d1-sul 20 p41 so00 output d0-uf 21 p42 sck00 i/o yes n-ch open-drain output can be selected. d2-sufl note software pull-up function caution p40 and p42 have hysteresis characteristics when th e alternate function is input, but not in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 96 (1) port 4 register (p4) 0 0 is output 1 is output p4n 0 1 control of output data (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 control of i/o mode (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h (3) port 4 mode control register (pmc4) 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sck00 i/o pmc42 0 1 specification of p42 pin operation mode i/o port so00 output pmc41 0 1 specification of p41 pin operation mode i/o port si00 input pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h chapter 4 port functions preliminary user?s manual u16895ej1v0ud 97 (4) port 4 function register (pf4) 0 normal output n-ch open-drain output pf4n 0 1 control of normal output/n-ch open-drain output (n = 1, 2) pf4 0 0 0 0 pf42 pf41 0 after reset: 00h r/w address: fffffc68h caution when using p41 and p42 as n-ch open- drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p4n bit = 1 pf4n bit = 1 pmc4n bit = 1 (5) pull-up resistor option register 4 (pu4) 0 not connected connected pu4n 0 1 control of on-chip pull-up resistor connection (n = 0 to 2) pu4 0 0 0 0 pu42 pu41 pu40 after reset: 00h r/w address: fffffc48h chapter 4 port functions preliminary user?s manual u16895ej1v0ud 98 4.3.4 port 5 port 5 is a 6-bit i/o port for which i/o se ttings can be controll ed in 1-bit units. port 5 includes the following alternate functions. table 4-7. alternate-function pins of port 5 pin no. pin name alternate function i/o pull note remark block type 32 p50 ti011/rtp00/kr0 i/o e10-sult 33 p51 ti50/rtp01/kr1 i/o e10-sult 34 p52 to50/rtp02/kr2 i/o e00-sut 35 p53 sia0/rtp03/kr3 i/o ? e10-sult 36 p54 soa0/rtp04/kr4 i/o e00-suft 37 p55 scka0/rtp05/kr5 i/o yes n-ch open-drain output can be selected. e20-suflt note software pull-up function (1) port 5 register (p5) 0 is output 1 is output p5n 0 1 control of output data (in output mode) (n = 0 to 5) p5 after reset: 00h (output latch) r/w address: fffff40ah 0 0 p55 p54 p53 p52 p51 p50 (2) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 control of i/o mode (n = 0 to 5) 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah pm5 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 99 (3) port 5 mode control register (pmc5) i/o port/kr5 input scka0 i/o/rtp05 output pmc55 0 1 specification of p55 pin operation mode i/o port/kr4 input soa0 output/rtp04 output pmc54 0 1 specification of p54 pin operation mode 0 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 after reset: 00h r/w address: fffff44ah pmc5 i/o port/kr3 input sia0 input/rtp03 output pmc53 0 1 specification of p53 pin operation mode i/o port/kr2 input to50 output/rtp02 output pmc52 0 1 specification of p52 pin operation mode i/o port/kr1 input ti50 input/rtp01 output pmc51 0 1 specification of p51 pin operation mode i/o port/kr0 input ti011 input/rtp00 output pmc50 0 1 specification of p50 pin operation mode (4) port 5 function register 5 (pf5) 0 normal output n-ch open-drain output pf5n 0 1 control of normal output/n-ch open-drain output (n = 4, 5) pf5 0 pf55 pf54 0 0 0 0 after reset: 00h r/w address: fffffc6ah cautions 1. always set bits 0 to 3, 6, and 7 of the pf5 register to 0. 2. when using p54 and p55 as n-ch open-dr ain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p5n bit = 1 pf5n bit = 1 pmc5n bit = 1 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 100 (5) port 5 function control register (pfc5) pfc5 scka0 i/o rtp05 output pfc55 0 1 specification of alternate-function pin of p55 pin sia0 input rtp03 output pfc53 0 1 specification of alternate-function pin of p53 pin soa0 output rtp04 output pfc54 0 1 specification of alternate-function pin of p54 pin after reset: 00h r/w address: fffff46ah 0 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 to50 output rtp02 output pfc52 0 1 specification of alternate-function pin of p52 pin ti50 input rtp01 output pfc51 0 1 specification of alternate-function pin of p51 pin ti011 input rtp00 output pfc50 0 1 specification of alternate-function pin of p50 pin (6) pull-up resistor option register 5 (pu5) 0 not connected connected pu5n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) 0 pu55 pu54 pu53 pu52 pu51 pu50 after reset: 00h r/w address: fffffc4ah pu5 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 101 4.3.5 port 7 port 7 is an 8-bit input-only port for which all the pins are fixed to input. port 7 includes the following alternate functions. table 4-8. alternate-function pins of port 7 pin no. pin name alternate function i/o pull note remark block type 80 p70 ani0 input a-a 79 p71 ani1 input a-a 78 p72 ani2 input a-a 77 p73 ani3 input a-a 76 p74 ani4 input a-a 75 p75 ani5 input a-a 74 p76 ani6 input a-a 73 p77 ani7 input no ? a-a note software pull-up function (1) port 7 register (p7) input low level input high level p7n 0 1 input data read (n = 0 to 7) after reset: undefined r address: fffff40eh p77 p76 p75 p74 p73 p72 p71 p70 p7 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 102 4.3.6 port 9 port 9 is a 9-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 9 includes the following alternate functions. table 4-9. alternate-function pins of port 9 pin no. pin name alternate function i/o pull note remark block type 38 p90 txd1/kr6 i/o ex0-sut 39 p91 rxd1/kr7 input ex1-suht 40 p96 ti51/to51 i/o ex0-sut 41 p97 si01 input ? ex1-sul 42 p98 so01 output ex0-uf 43 p99 sck01 i/o n-ch open-drain output can be specified. ex2-sufl 44 p913 intp4 input ex1-suil 45 p914 intp5 input ex1-suil 46 p915 intp6 input no analog noise elimination ex1-suil note software pull-up function caution p97, p99, and p913 to p915 have hysteresis characteristics when the alternate function is input, but not in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 103 (1) port 9 register (p9) 0 is output 1 is output p9n 0 1 control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15) after reset: 00h (output latch) r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p915 p9 (p9h note ) p914 p913 0 0 0 p99 p98 p97 p96 0 0 0 0 p91 p90 8 9 10 11 12 13 14 15 (p9l) note when reading from or writing to bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p9h register. remark the p9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lower 8 bits of the p9 register are used as the p9h register and as the p9l register, re spectively, these registers can be read or written in 8-bit or 1-bit units. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 control of i/o mode (n = 0, 1, 6 to 9, 13 to 15) pm96 1 1 1 1 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm9 (pm9h note ) pm914 pm913 1 1 1 pm99 pm98 8 9 10 11 12 13 14 15 (pm9l) note when reading from or writing to bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. remark the pm9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pm9 register are used as the pm9h register and as the pm9l register, re spectively, this register can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 104 (3) port 9 mode control register (pmc9) i/o port intp6 input pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 0 0 0 0 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc9 (pmc9h note ) pmc914 pmc913 0 0 0 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port intp5 input pmc914 0 1 specification of p914 pin operation mode i/o port sck01 i/o pmc99 0 1 specification of p99 pin operation mode i/o port intp4 input pmc913 0 1 specification of p913 pin operation mode i/o port so01 output pmc98 0 1 specification of p98 pin operation mode (pmc9l) i/o port si01 input pmc97 0 1 specification of p97 pin operation mode i/o port/ti51 input to51 output pmc96 0 1 specification of p96 pin operation mode i/o port/kr7 input rxd1 input pmc91 0 1 specification of p91 pin operation mode i/o port/kr6 input txd1 output pmc90 0 1 specification of p90 pin operation mode note when reading from or writing to bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. remark the pmc9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pmc9 register are used as the pmc9h register and as the pmc9l r egister, respectively, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 105 (4) port 9 function register h (pf9h) 0 normal output n-ch open-drain output pf9n 0 1 control of normal output/n-ch open-drain output (n = 8, 9) pf9h 0 0 0 0 0 pf99 pf98 after reset: 00h r/w address: fffffc73h caution when using p98 and p99 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 be fore setting the pin to n-ch open-drain output. p9n bit = 1 pfc9n bit = 0/1 pf9n bit = 1 pmc9n bit = 1 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 106 (5) port 9 function control register (pfc9) caution when port 9 is sp ecified as an alternate function by the pmc9.pmc9n bit with the pfc9n bit maintaining the initial value (0), output becom es undefined. therefore, to specify port 9 as alternate function 2, set the pfc9 n bit to 1 first and then set the pmc9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15). pfc9 (pfc9h note ) intp6 input pfc915 1 specification of alternate-function pin of p915 pin intp5 input pfc914 1 specification of alternate-function pin of p914 pin intp4 input pfc913 1 specification of alternate-function pin of p913 pin after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 0 0 0 0 pfc91 pfc90 pfc915 pfc914 pfc913 0 0 0 pfc99 pfc98 8 9 10 11 12 13 14 15 sck01 i/o pfc99 1 specification of alternate-function pin of p99 pin so01 output pfc98 1 specification of alternate-function pin of p98 pin (pfc9l) si01 input pfc97 1 specification of alternate-function pin of p97 pin to51 output pfc96 1 specification of alternate-function pin of p96 pin rxd1 input pfc91 1 specification of alternate-function pin of p91 pin txd1 output pfc90 1 specification of alternate-function pin of p90 pin note when reading from or writing to bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. remark the pfc9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pfc9 register are used as the pfc9h register and as t he pfc9l register, respective ly, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 107 (6) pull-up resistor option register 9 (pu9) not connected connected pu9n 0 1 control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15) pu9 (pu9h note ) after reset: 0000h r/w address: pu9 fffffc52h, pu9l fffffc52h, pu9h fffffc53h pu97 pu96 0 0 0 0 pu91 pu90 pu915 pu914 pu913 0 0 0 pu99 pu98 8 9 10 11 12 13 14 15 (pu9l) note when reading from or writing to bits 8 to 15 of the pu9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu9h register. remark the pu9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pu9 register are used as the pu9h register and as the pu9l register, respectively, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 108 4.3.7 port cm port cm is a 4-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port cm includes the following alternate functions. table 4-10. alternate-function pins of port cm pin no. pin name alternate function i/o pull note remark block type 49 pcm0 wait input d1-uh 50 pcm1 clkout output d0-u 51 pcm2 hldak output d0-u 52 pcm3 hldrq input yes ? d1-uh note software pull-up function (1) port cm register (pcm) 0 is output 1 is output pcmn 0 1 control of output data (in output mode) (n = 0 to 3) after reset: 00h (output latch) r/w address: fffff00ch 0 pcm 0 0 0 pcm3 pcm2 pcm1 pcm0 (2) port cm mode register (pmcm) output mode input mode pmcmn 0 1 control of i/o mode (n = 0 to 3) after reset: ffh r/w address: fffff02ch 1 pmcm 1 1 1 pmcm3 pmcm2 pmcm1 pmcm0 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 109 (3) port cm mode control register (pmccm) 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldrq input pmccm3 0 1 specification of pcm3 pin operation mode i/o port hldak output pmccm2 0 1 specification of pcm2 pin operation mode i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch (4) pull-up resistor option register cm (pucm) not connected connected pucmn 0 1 control of on-chip pull-up resistor connection (n = 0 to 3) after reset: 00h r/w address: ffffff4ch 0 pucm 0 0 0 pucm3 pucm2 pucm1 pucm0 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 110 4.3.8 port cs port cs is a 2-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port cs includes the following alternate functions. table 4-11. alternate-function pins of port cs pin no. pin name alternate function i/o pull note remark block type 47 pcs0 cs0 output d0-uz 48 pcs1 cs1 output yes ? d0-uz note software pull-up function (1) port cs register (pcs) 0 is output 1 is output pcsn 0 1 control of output data (in output mode) (n = 0, 1) after reset: 00h (output latch) r/w address: fffff008h 0 pcs 0 0 0 0 0 pcs1 pcs0 (2) port cs mode register (pmcs) 0 output mode input mode pmcsn 0 1 control of i/o mode (n = 0, 1) pmcs 0 0 0 0 0 pmcs1 pmcs0 after reset: ffh r/w address: fffff028h chapter 4 port functions preliminary user?s manual u16895ej1v0ud 111 (3) port cs mode control register (pmccs) 0 i/o port csn output pmccsn 0 1 specification of pcsn pin operation mode (n = 0, 1) pmccs 0 0 0 0 0 pmccs1 pmccs0 after reset: 00h r/w address: fffff048h (4) pull-up resistor option register cs (pucs) 0 not connected connected pucsn 0 1 control of on-chip pull-up resistor connection (n = 0, 1) pucs 0 0 0 0 0 pucs1 pucs0 after reset: 00h r/w address: ffffff48h chapter 4 port functions preliminary user?s manual u16895ej1v0ud 112 4.3.9 port ct port ct is a 4-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port ct includes the following alternate functions. table 4-12. alternate-function pins of port ct pin no. pin name alternate function i/o pull note remark block type 53 pct0 wr0 output d0-uz 54 pct1 wr1 output d0-uz 55 pct4 rd output d0-uz 56 pct6 astb output yes ? d0-uz note software pull-up function (1) port ct register (pct) 0 0 is output 1 is output pctn 0 1 control of output data (in output mode) (n = 0, 1, 4, 6) pct pct6 0 pct4 0 0 pct1 pct0 after reset: 00h (output latch) r/w address: fffff00ah (2) port ct mode register (pmct) 0 output mode input mode pmctn 0 1 control of i/o mode (n = 0, 1, 4, 6) pmct pmct6 0 pmct4 0 0 pmct1 pmct0 after reset: ffh r/w address: fffff02ah chapter 4 port functions preliminary user?s manual u16895ej1v0ud 113 (3) port ct mode control register (pmcct) 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specification of pct6 pin operation mode i/o port rd output pmcct4 0 1 specification of pct4 pin operation mode i/o port wr1 output pmcct1 0 1 specification of pct1 pin operation mode i/o port wr0 output pmcct0 0 1 specification of pct0 pin operation mode after reset: 00h r/w address: fffff04ah (4) pull-up resistor option register ct (puct) 0 not connected connected puctn 0 1 control of on-chip pull-up resistor connection (n = 0, 1, 4, 6) puct puct6 0 puct4 0 0 puct1 puct0 after reset: 00h r/w address: ffffff4ah chapter 4 port functions preliminary user?s manual u16895ej1v0ud 114 4.3.10 port dl port dl is a 16-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port dl includes the following alternate functions. table 4-13. alternate-function pins of port dl pin no. pin name alternate function i/o pull note remark block type 57 pdl0 ad0 i/o d2-ulz 58 pdl1 ad1 i/o d2-ulz 59 pdl2 ad2 i/o d2-ulz 60 pdl3 ad3 i/o d2-ulz 61 pdl4 ad4 i/o d2-ulz 62 pdl5 ad5 i/o d2-ulz 63 pdl6 ad6 i/o d2-ulz 64 pdl7 ad7 i/o d2-ulz 65 pdl8 ad8 i/o d2-ulz 66 pdl9 ad9 i/o d2-ulz 67 pdl10 ad10 i/o d2-ulz 68 pdl11 ad11 i/o d2-ulz 69 pdl12 ad12 i/o d2-ulz 70 pdl13 ad13 i/o d2-ulz 71 pdl14 ad14 i/o d2-ulz 72 pdl15 ad15 i/o yes ? d2-ulz note software pull-up function chapter 4 port functions preliminary user?s manual u16895ej1v0ud 115 (1) port dl register (pdl) pdl15 0 is output 1 is output pdln 0 1 control of output data (in output mode) (n = 0 to 15) pdl (pdlh note ) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: 00h (output latch) r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 (pdll) note when reading from or writing to bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pdlh register. remark the pdl register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the pdl register are used as the pdlh register and as the pdll register, respectively, these registers can be read or written in 8-bit or 1-bit units. (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 control of i/o mode (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h pmdl15 pmdl (pmdlh note ) pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 (pmdll) note when reading from or writing to bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmdlh register. remark the pmdl register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the pmdl register are used as the pmdlh register and as the pmdll r egister, respectively, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 116 (3) port dl mode control register (pmcdl) i/o port adn i/o (address/data bus i/o) pmcdln 0 1 specification of pdln pin operation mode (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h pmcdl15 pmcdl (pmcdlh note ) pmcdl14 pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 (pmcdll) note when reading from or writing to bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmcdlh register. caution when specifying the por t/alternate function for each bi t, pay careful attention to the operation of the alternate functions. remark the pmcdl register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pmcdl register are used as the pmcdlh register and as the pmcdll register, respectively, these registers can be read or written in 8-bit or 1-bit units. (4) pull-up resistor option register dl (pudl) not connected connected pudln 0 1 control of on-chip pull-up resistor connection (n = 0 to 15) pudl7 pudl6 pudl5 pudl4 pudl3 pudl2 pudl1 pudl0 after reset: 0000h r/w address: pudl ffffff44h, pudll ffffff44h, pudlh ffffff45h pudl15 pudl (pudlh note ) pudl14 pudl13 pudl12 pudl11 pudl10 pudl9 pudl8 8 9 10 11 12 13 14 15 (pudll) note when reading from or writing to bits 8 to 15 of the pudl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pudlh register. remark the pudl register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pudl register are used as the pudlh register and as the pudll r egister, respectively, these registers can be read or written in 8-bit or 1-bit units. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 117 4.4 block diagrams figure 4-2. block diagram of type a-a internal bus rd a/d input signal pmn p-ch n-ch chapter 4 port functions preliminary user?s manual u16895ej1v0ud 118 figure 4-3. block diagram of type d0-u wr pmc rd address output signal of alternate function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch output latch (pmn) internal bus selector selector selector chapter 4 port functions preliminary user?s manual u16895ej1v0ud 119 figure 4-4. block diagram of type d0-uf wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch address output latch (pmn) internal bus selector selector selector output signal of alternate function 1 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 120 figure 4-5. block diagram of type d0-uz wr pmc rd wr port pmn pmcmn wr pu pumn wr pm address pmmn output latch (pmn) ev dd p-ch internal bus selector selector selector output signal of alternate function 1 output buffer off signal remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 121 figure 4-6. block diagram of type d1-suil wr pmc rd address input signal of alternate function 1 wr port pmn note 2 pmcmn wr intf intfmn note 1 wr pu pumn wr pm pmmn detection of noise elimination edge wr intr intrmn note 1 ev dd p-ch output latch (pmn) internal bus selector selector notes 1. refer to 19.4 external interrupt request input pins (nmi, intp0 to intp7) . 2. there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 122 figure 4-7. block diagram of type d1-suihl wr pmc rd address wr port pmn pmcmn wr pu pumn wr pm pmmn wr intf intfmn note 1 wr intr intrmn note 1 ev dd p-ch input signal of alternate function 1-2 input signal of alternate function 1-1 detection of noise elimination edge output latch (pmn) note 2 internal bus selector selector notes 1. refer to 19.4 external interrupt request input pins (nmi, intp0 to intp7) . 2. there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 123 figure 4-8. block diagram of type d1-sul wr pmc rd wr port address pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch note output latch (pmn) internal bus selector selector input signal of alternate function 1 note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 124 figure 4-9. block diagram of type d1-uh wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch address output latch (pmn) internal bus selector selector input signal of alternate function 1 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 125 figure 4-10. block diag ram of type d2-snmufh wr pmc rd address output signal of alternate function 1 input signal of alternate function 1 wr port pmcmn wr pf pfmn wr pm pmmn pmn ev dd ev ss note mask option n-ch output latch (pmn) internal bus selector selector selector note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 126 figure 4-11. block diagram of type d2-sufl wr pmc rd note wr port pmn pmcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch address output latch (pmn) internal bus selector selector selector input signal of alternate function 1 output signal of alternate function 1 output enable signal of alternate function 1 note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 127 figure 4-12. block diagram of type d2-ulz wr pmc rd wr port pmn pmcmn wr pm pmmn wr pu pumn bv dd p-ch address output latch (pmn) internal bus selector selector selector output enable signal of alternate function 1 output signal of alternate function 1 input enable signal of alternate function 1 input signal of alternate function 1 output buffer off signal remark output buffer off signal: signal that is asserted in the idle or stop mode, or when the bus is held. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 128 figure 4-13. block diagram of type e00-suft wr pmc rd address alternate-function input signal in port mode output signal of alternate function 2 wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) internal bus selector selector selector selector output signal of alternate function 1 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 129 figure 4-14. block diagram of type e00-sut wr pmc rd address alternate-function input signal in port mode output signal of alternate function 2 output signal of alternate function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector selector chapter 4 port functions preliminary user?s manual u16895ej1v0ud 130 figure 4-15. block diagram of type e10-sul wr pmc rd address input signal of alternate function 1 output signal of alternate function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector note note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 131 figure 4-16. block diagram of type e10-sult wr pmc rd address alternate-function input signal in port mode input signal of alternate function 1 output signal of alternate function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector chapter 4 port functions preliminary user?s manual u16895ej1v0ud 132 figure 4-17. block diagram of type e20-suflt wr pmc rd wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch address output latch (pmn) internal bus selector selector selector selector output signal of alternate function 2 output enable signal of alternate function 1 output signal of alternate function 1 input signal of alternate function 1 alternate-function input signal in port mode chapter 4 port functions preliminary user?s manual u16895ej1v0ud 133 figure 4-18. block diagram of type ex0-sut wr pmc rd address alternate-function input signal in port mode output signal of alternate function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector chapter 4 port functions preliminary user?s manual u16895ej1v0ud 134 figure 4-19. block diag ram of type ex0-uf wr pmc rd address output signal of alternate function 2 wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) internal bus selector selector selector chapter 4 port functions preliminary user?s manual u16895ej1v0ud 135 figure 4-20. block diag ram of type ex1-suht wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) address input signal of alternate function 2 alternate-function input signal in port mode internal bus selector selector chapter 4 port functions preliminary user?s manual u16895ej1v0ud 136 figure 4-21. block diag ram of type ex1-suil wr pmc rd wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr intf intfmn note 1 wr intr intrmn note 1 ev dd p-ch output latch (pmn) note 2 address input signal of alternate function 2 detection of noise elimination edge internal bus selector selector notes 1. refer to 19.4 external interrupt request input pins (nmi, intp0 to intp7) . 2. there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 137 figure 4-22. block diagram of type ex1-sul wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) address input signal of alternate function 2 internal bus selector selector chapter 4 port functions preliminary user?s manual u16895ej1v0ud 138 figure 4-23. block diagram of type ex2-sufl wr pmc rd address input signal of alternate function 2 output signal of alternate function 2 wr port pmn note pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) output enable signal of alternate function 2 internal bus selector selector selector note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 139 figure 4-24. block diagram of type g1010-sul p-ch wr pmc rd address note input signal of alternate function 1 input signal of alternate function 3 output signal of alternate function 2 output signal of alternate function 4 wr port pmn pmcmn wr pfce pfcemn wr pm pmmn wr pfc pfcmn wr pu pumn ev dd output latch (pmn) internal bus selector selector selector selector note there are no hysteresis characteristics in the port mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 140 4.5 port register setting when alternate function is used table 4-14 shows the port register settings when each port is used for an alternate function. when using a port pin as an alternate-functi on pin, refer to description of each pin. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 141 table 4-14. settings when port pins are used for alternate functions (1/5) other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? pfc03 = 0 ? ? ? note 1 note 1 , pfc31 = 0 note 2 , pfc32 = 0 note 2 , pfc32 = 0 pfc32 = 1 pfcenx bit of pfcen register ? ? ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmc00 = 1 pmc01 = 1 pmc02 = 1 pmc03 = 1 pmc04 = 1 pmc05 = 1 pmc06 = 1 pmc30 = 1 pmc31 = 1 pmc31 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmnx bit of pmn register pm00 = setting not required pm01 = setting not required pm02 = setting not required pm03 = setting not required pm04 = setting not required pm05 = setting not required pm06 = setting not required pm30 = setting not required pm31 = setting not required pm31 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pnx bit of pn register p00 = setting not required p01 = setting not required p02 = setting not required p03 = setting not required p04 = setting not required p05 = setting not required p06 = setting not required p30 = setting not required p31 = setting not required p31 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required i/o output output input input input input input output input input input input output alternate function function name toh0 toh1 nmi intp0 intp1 intp2 intp3 txd0 rxd0 intp7 asck0 adtrg to01 pin name p00 p01 p02 p03 p04 p05 p06 p30 p31 p32 ? ? ? ? ? pfc33 = 0 pfc33 = 1 pfc33 = 0 pfc33 = 1 pfce33 = 0 pfce33 = 0 pfce33 = 1 pfce33 = 1 pmc33 = 1 pmc33 = 1 pmc33 = 1 pm33 = setting not required pm33 = setting not required pm33 = setting not required pm33 = setting not required p33 = setting not required p33 = setting not required p33 = setting not required p33 = setting not required input output input output ti000 to00 tip00 top00 p33 pmc33 = 1 notes 1. the intp7 and rxd0 pins are alternate-function pins. when usi ng the pin as the rxd0 pin, dis able edge detection of the altern ate-function intp7 pin (clear the intf3.intf31 and intr3.intr31 bits to 0). when using the pin as the intp7 pin, stop the uart 0 receive operation (clear the asim0.rxe0 bit to 0). 2. the asck0 and adtrg pins are alternate-function pins. when usi ng the pin as the asck0 pin, disa ble the trigger input of the a lternate-function adtrg pin (clear the ads.trg bit to 0 or set the ads.adtmd bit to 1). when using the pin as the adtrg pin, do not set the uart0 oper ation clock to external input (set the cksr0.tps03 to cksr 0.tps00 bits to other than 1011). chapter 4 port functions preliminary user?s manual u16895ej1v0ud 142 table 4-14. settings when port pins are used for alternate functions (2/5) ? ? ? ? ? ? ? ? ? ? ? pfc34 = 0 pfc34 = 1 pfc34 = 0 pfc34 = 1 pfc35 = 0 pfc35 = 1 ? ? ? pfce34 = 0 pfce34 = 0 pfce34 = 1 pfce34 = 1 ? ? ? ? ? ? ? pmc34 = 1 pmc34 = 1 pmc34 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pmc38 = 1 pmc39 = 1 pmc40 = 1 pmc41 = 1 pmc42 = 1 pm34 = setting not required pm34 = setting not required pm34 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required pm38 = setting not required pm39 = setting not required pm40 = setting not required pm41 = setting not required pm42 = setting not required p34 = setting not required p34 = setting not required p34 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required p38 = setting not required p39 = setting not required p40 = setting not required p41 = setting not required p42 = setting not required input output input output input output i/o i/o input output i/o ti001 to00 tip10 top10 ti010 to01 sda0 note scl0 note si00 so00 p34 p35 p38 p39 p40 p41 p42 sck00 other bits (registers) pfcnx bit of pfcn register pfcenx bit of pfcen register pmcnx bit of pmcn register pmnx bit of pmn register pnx bit of pn register i/o alternate function function name pin name ? ? note only in the chapter 4 port functions preliminary user?s manual u16895ej1v0ud 143 table 4-14. settings when port pins are used for alternate functions (3/5) ? ? krm0 (krm) = 1 ? ? krm1 (krm) = 1 ? ? krm2 (krm) = 1 ? ? krm3 (krm) = 1 pf54 (pf5) = don?t care pf54 (pf5) = 0 pf54 (pf5) = 0, krm4 (krm) = 1 pf55 (pf5) = don?t care pf55 (pf5) = 0 pf55 (pf5) = 0, krm5 (krm) = 1 ? ? ? ? ? ? ? ? pfc50 = 0 pfc50 = 1 pfc50 = 0 pfc51 = 0 pfc51 = 1 pfc51 = 0 pfc52 = 0 pfc52 = 1 pfc52 = 0 pfc53 = 0 pfc53 = 1 pfc53 = 0 pfc54 = 0 pfc54 = 1 pfc54 = 0 pfc55 = 0 pfc55 = 1 pfc55 = 0 ? ? ? ? ? ? ? ? pmc50 = 1 pmc50 = 1 pmc50 = 0 pmc51 = 1 pmc51 = 1 pmc51 = 0 pmc52 = 1 pmc52 = 1 pmc52 = 0 pmc53 = 1 pmc53 = 1 pmc53 = 0 pmc54 = 1 pmc54 = 1 pmc54 = 0 pmc55 = 1 pmc55 = 1 pmc55 = 0 ? ? ? ? ? ? ? ? pm50 = setting not required pm50 = setting not required pm50 = 1 pm51 = setting not required pm51 = setting not required pm51 = 1 pm52 = setting not required pm52 = setting not required pm52 = 1 pm53 = setting not required pm53 = setting not required pm53 = 1 pm54 = setting not required pm54 = setting not required pm54 = 1 pm55 = setting not required pm55 = setting not required pm55 = 1 ? ? ? ? ? ? ? ? p50 = setting not required p50 = setting not required p50 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required input output input input output input output output input input output input output output input i/o output input input input input input input input input input ti011 rtp00 kr0 ti50 rtp01 kr1 to50 rtp02 kr2 sia0 rtp03 kr3 soa0 rtp04 kr4 scka0 rtp05 kr5 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 p50 p51 p52 p53 p54 p55 p70 p71 p72 p73 p74 p75 p76 p77 other bits (registers) pfcnx bit of pfcn register pmcnx bit of pmcn register pmnx bit of pmn register pnx bit of pn register i/o alternate function function name pin name chapter 4 port functions preliminary user?s manual u16895ej1v0ud 144 table 4-14. settings when port pins are used for alternate functions (4/5) ? krm6 (krm) = 1 ? krm7 (krm) = 1 ? ? ? pf98 (pf9) = don?t care pf98 (pf9) = don?t care pfc90 = 1 pfc90 = 0 pfc91 = 1 pfc91 = 0 pfc96 = 0 pfc96 = 1 pfc97 = 1 pfc98 = 1 pfc99 = 1 pmc90 = 1 pmc90 = 0 pmc91 = 1 pmc91 = 0 pmc96 = 0 pmc96 = 1 pmc97 = 1 pmc98 = 1 pmc99 = 1 pm90 = setting not required pm90 = 1 pm91 = setting not required pm91 = 1 pm96 = 1 pm96 = setting not required pm97 = setting not required pm98 = setting not required pm99 = setting not required p90 = setting not required p90 = setting not required p91 = setting not required p91 = setting not required p96 = setting not required p96 = setting not required p97 = setting not required p98 = setting not required p99 = setting not required output input input input input output input output i/o txd1 kr6 rxd1 kr7 ti51 to51 si01 so01 sck01 p90 p91 p96 p97 p98 p99 other bits (registers) pfcnx bit of pfcn register pmcnx bit of pmcn register pmnx bit of pmn register pnx bit of pn register i/o alternate function function name pin name ? ? ? pfc913 = 1 pfc914 = 1 pfc915 = 1 pmc913 = 1 pmc914 = 1 pmc915 = 1 pm913 = setting not required pm914 = setting not required pm915 = setting not required p913 = setting not required p914 = setting not required p915 = setting not required input input input intp4 intp5 intp6 p913 p914 p915 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmccm0 = 1 pmccm1 = 1 pmccm2 = 1 pmccm3 = 1 pmccs0 = 1 pmccs1 = 1 pmcct0 = 1 pmcct1 = 1 pmcct4 = 1 pmcct6 = 1 pmcm0 = setting not require pmcm1 = setting not require pmcm2 = setting not require pmcm3 = setting not require pmcs0 = setting not required pmcs1 = setting not required pmct0 = setting not required pmct1 = setting not required pmct4 = setting not required pmct6 = setting not required pcm0 = setting not required pcm1 = setting not required pcm2 = setting not required pcm3 = setting not required pcs0 = setting not required pcs1 = setting not required pct0 = setting not required pct1 = setting not required pct4 = setting not required pct6 = setting not required input output output input output output output output output output wait clkout hldak hldrq cs0 cs1 wr0 wr1 rd astb pcm0 pcm1 pcm2 pcm3 pcs0 pcs1 pct0 pct1 pct4 pct6 chapter 4 port functions preliminary user?s manual u16895ej1v0ud 145 table 4-14. settings when port pins are used for alternate functions (5/5) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 pmdl0 = setting not required pmdl1 = setting not required pmdl2 = setting not required pmdl3 = setting not required pmdl4 = setting not required pmdl5 = setting not required pmdl6 = setting not required pmdl7 = setting not required pmdl8 = setting not required pmdl9 = setting not required pmdl10 = setting not required pmdl11 = setting not required pmdl12 = setting not required pmdl13 = setting not required pmdl14 = setting not required pmdl15 = setting not required pdl0 = setting not required pdl1 = setting not required pdl2 = setting not required pdl3 = setting not required pdl4 = setting not required pdl5 = setting not required pdl6 = setting not required pdl7 = setting not required pdl8 = setting not required pdl9 = setting not required pdl10 = setting not required pdl11 = setting not required pdl12 = setting not required pdl13 = setting not required pdl14 = setting not required pdl15 = setting not required i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 other bits (registers) pfcnx bit of pfcn register pmcnx bit of pmcn register pmnx bit of pmn register pnx bit of pn register i/o alternate function function name pin name chapter 4 port functions preliminary user?s manual u16895ej1v0ud 146 4.6 cautions 4.6.1 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. chapter 4 port functions preliminary user?s manual u16895ej1v0ud 147 4.6.2 hysteresis characteristics in port mode, the following ports do not have hysteresis characteristics. p02 to p06 p31 to p35, p38, p39 p40, p42 p97, p99, p913 to p915 preliminary user?s manual u16895ej1v0ud 148 chapter 5 bus control function the v850es/kf1+ is provided with an external bus interf ace function by which external memories such as rom and ram, and i/o c an be connected. 5.1 features { output is possible from a multiple x bus with a minimum of 3 bus cycles { chip select function for up to 2 spaces { 8-bit/16-bit data bus selectable (for each ar ea selected by chip select function) { wait function ? programmable wait function of up to 7 states (selecta ble for each area selected by chip select function) ? external wait function using wait pin { idle state function { bus hold function chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 149 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus wait pcm0 input external wait control clkout pcm1 output internal system clock output cs0, cs1 pcs0, pcs1 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control 5.2.1 pin status when intern al rom, internal ram, or on -chip peripheral i/o is accessed when the internal rom, internal ram, or on-chip peripheral i/o is accessed, the status of each pin is as follows. table 5-2. pin statuses when in ternal rom, internal ram, or on -chip peripheral i/o is accessed address/data bus (ad15 to ad0) undefined control signal inactive caution when a write access is performed to the inte rnal rom area, address, data, and control signals are activated in the same way as ac cess to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850es/kf 1+ in each operation mode, refer to 2.2 pin status . chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 150 5.3 memory block function the 64 mb memory space is divided into chip select areas of (lower) 64 kb and 64 kb. the programmable wait function and bus cycle operati on mode for each of these chip select areas can be i ndependently controlled. figure 5-1. data memory map: physical address 3ffffffh 3fec000h 3febfffh 0210000h 020ffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 3ffd800h 3ffd7ffh 3fff000h 3ffefffh 3ffffffh 0000000h 3fec000h (80 kb) use-prohibited area internal rom area note 2 (1 mb) external memory area (64 kb) internal ram area (6 kb note 1 ) on-chip peripheral i/o area (4 kb) use-prohibited area external memory area (64 kb) (2 mb) cs0 cs1 setting prohibited 0110000h 010ffffh notes 1. pd703308, 703308y, 70f3 308, 70f3308y: 16 kb (3ffb000h to 3ffefffh) 2. this area is an external memory area in the case of a data write access. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 151 5.3.1 chip select control function of the 64 mb (linear) address space, two 64 kb s paces (0100000h to 010ffffh /0200000h to 020ffffh) include two chip select control functions, cs0 and cs1. the areas that can be selected by cs0 and cs1 are fixed. by using these chip select control func tions, the memory space can be used effect ively. the allocation of the chip select areas is shown in the table below. cs0 0100000h to 010ffffh (64 kb) cs1 0200000h to 020ffffh (64 kb) chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 152 5.4 bus access 5.4.1 number of clocks for access the following table shows the number of base clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) on-chip peripheral i/o (16 bits) instruction fetch (normal access) 1 1 note 1 3 + n ? ? chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 153 5.4.3 access by bus size the v850es/kf1+ accesses the on-chip per ipheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/kf1+ supports only the little endian format. figure 5-2. little endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/kf1+ has an address misalign function. with this function, data can be placed at all addresse s, regardless of the format of the data (word data or halfword data). however, if the word data or halfwor d data is not aligned at the boundary, a bus cycle is generated at least twice, causi ng the bus efficiency to drop. (a) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (b) word-length data access (i) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) a halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 154 (2) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 155 (3) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 2n address address 2n + 1 halfword data external data bus halfword data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 156 (4) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 address address address word data external data bus word data external data bus word data external data bus chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 157 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 address address word data external data bus word data external data bus <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 address address address word data external data bus word data external data bus word data external data bus chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 158 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address address address address word data external data bus word data external data bus word data external data bus <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 address address address address word data external data bus word data external data bus word data external data bus word data external data bus chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 159 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access address address address address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 word data external data bus word data external data bus word data external data bus word data external data bus <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 address address address address word data external data bus word data external data bus word data external data bus word data external data bus chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 160 5.5 wait function 5.5.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-s peed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each cs space. the number of wait states can be pr ogrammed by using the dw c0 register. immediately after system reset, 7 data wait states are inserted fo r all the chip select areas. the dwc0 register can be read or written in 16-bit units. after reset, dwc0 is set to 7777h. cautions 1. the internal rom and internal ram ar eas are not subject to programmable wait, and are always accessed without a wait state. the on-chip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, an d then do not change the set values. also, do not access an external memory area until the initial settings of the dwc0 register are complete. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 0/1 note dw12 0/1 note dw11 0/1 note dw10 0 0 0/1 note dw02 0/1 note dw01 0/1 note dw00 8 9 10 11 12 13 number of wait states inserted in csn space (n = 0, 1) 14 15 1 2 3 4 5 6 7 0 cs0 csn signal cs1 note changing the value does not affect the operation. caution be sure to clear bi ts 15, 11, 7, and 3 to 0. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 161 5.5.2 external wait function to synchronize an extremely slow memory, i/o, or a synchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). access to each area of the internal rom, internal ram, a nd on-chip peripheral i/o is not subject to control by the external wait function, in the same ma nner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. 5.5.3 relationship between progr ammable wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specified by the set value of the programmable wait and t he wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the pr ogrammable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. example of inserting wait states clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 162 5.5.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the awc register. address wait insertion is set for each chip select area (cs0 and cs1). if an address setup wait is inserted, it seems that the high-clock period of t1 state is extended by 1 clock. if an address hold wait is inserted, it s eems that the low-clock period of t1 state is extended by 1 clock. (1) address wait cont rol register (awc) this register can be read or written in 16-bit units. after reset, awc is set to ffffh. cautions 1. the internal rom, internal ram, and on-chip peripher al i/o areas are not subject to address setup wait or ad dress hold wait insertion. 2. write the awc register after reset, and th en do not change the set values. also, do not access an external memory area until the in itial settings of the awc register are complete. after reset: ffffh r/w address: fffff488h 1 0/1 note ahwn 0 1 not inserted inserted awc 1 0/1 note 1 0/1 note 1 0/1 note 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 specifies insertion of address hold wait (n = 0, 1) 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address setup wait (n = 0, 1) cs0 csn signal cs1 note changing the value does not affect the operation. caution be sure to set bits 15 to 8 to 1. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 163 5.6 idle state insertion function to facilitate interfacing with low-speed memories, one idle st ate (ti) can be inserted afte r the t3 state in the bus cycle that is executed for each space selected by csn. by in serting idle states, the data out put float delay time of the memory can be secured during read access (an id le state cannot be inserted during write access). whether the idle state is to be inserted c an be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) this register can be read or written in 16-bit units. after reset, bcc is set to aaaah. cautions 1. the internal rom, in ternal ram, and on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and th en do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. after reset: aaaah r/w address: fffff48ah 1 0/1 note bcn1 0 1 not inserted inserted bcc 0 0 1 0/1 note 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0, 1) 14 15 1 2 3 4 5 6 7 0 cs0 csn signal cs1 note changing the value does not affect the operation. caution be sure to set bits 15, 13, 11 , and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 164 5.7 bus hold function 5.7.1 functional outline the hldrq and hldak functions are valid if the pcm2 and pcm3 pins are set to their alternate functions. when the hldrq pin is asserted (low level), indicating th at another bus master has re quested bus mastership, the external address/data bus goes into a hi gh-impedance state and is released (bus ho ld status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until a peripheral i/o register or the ex ternal memory is accessed. the bus hold status is indica ted by assertion (low level) of the hld ak pin. the bus hold function enables the configuration of mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing in which bus hold request not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 165 5.7.2 bus hold procedure the bus hold status transiti on procedure is shown below. <1> low-level input to hldrq pin acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status. <5> output low level from hldak pin <6> high-level input to hldrq pin acknowledged <7> output high level from hldak pin <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.7.3 operation in power save mode because the internal system clock is stopped in the st op and idle modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deasserted, the hldak pi n is also deasserted, and the bus hold status is cleared. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 166 5.8 bus priority bus hold, instruction fetch (branch), instruction fetch (s uccessive), and operand data access are executed in the external bus cycle. bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-3. bus priority priority external bus cycle bus master high bus hold external device operand data access cpu instruction fetch (branch) cpu low instruction fetch (successive) cpu chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 167 5.9 bus timing figure 5-4. multiplex bus read timi ng (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout astb cs1, cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-5. multiplex bus read timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout ad15 to ad8 astb cs1, cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 168 figure 5-6. multiplex bus write timi ng (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout astb cs1, cs0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active figure 5-7. multiplex bus writ e timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout ad15 to ad8 astb cs1, cs0 wait ad7 to ad0 wr1, wr0 chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 169 figure 5-8. multiplex bu s hold timing (bus size : 16 bits, 16-bit access) t1 a1 t2 t3 ti note th th th th ti note t1 t2 t3 d1 clkout hldrq hldak astb cs1, cs0 ad15 to ad0 rd undefined undefined a2 d2 11 11 note this idle state (ti) does not de pend on the bcc register settings. remarks 1. refer to table 2-2 pin operation status in operation modes for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance. figure 5-9. address wait timing (bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb ad15 to ad0 cs1, cs0 wait rd a1 t1 t2 clkout astb ad15 to ad0 cs1, cs0 wait rd d1 d1 a1 remarks 1. tasw (address setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance. chapter 5 bus control function preliminary user?s manual u16895ej1v0ud 170 5.10 cautions with the external bus function, signals may not be outpu t at the correct timing under the following conditions. preliminary user?s manual u16895ej1v0ud 171 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. { main clock oscillator ? f x = 2 mhz (f xx = 8 mhz, regc = v dd = 2.7 to 5.5 v, in pll mode) ? f x = 2 to 5 mhz (f xx = 8 to 20 mhz, regc = v dd = 4.5 to 5.5 v, in pll mode) ? f x = 2 mhz (f xx = 8 mhz, regc = capacitor, v dd = 4.0 to 5.5 v, in pll mode) ? f x = 2 to 8 note mhz (f xx = 2 to 8 note mhz, regc = v dd = 2.7 to 5.5 v, in clock-through mode) { subclock oscillator ? 32.768 khz { on-chip ring oscillator (ring-osc) ? f r = 120 to 480 khz (240 khz (typ.)) { multiplication ( 4) function by pll (phase locked loop) ? clock-through mode/pll mode selectable ? usable voltage: v dd = 2.7 to 5.5 v { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) ? operates at f r after the reset signal for the clock monitor is generated upon detection of main clock stop. { peripheral clock generation { clock output function note this value may change after evaluation. remark f x : main clock oscillation frequency f xx : main clock frequency f r : ring-osc clock frequency chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 172 6.2 configuration figure 6-1. clock generator ring-osc intbrg clkout x1 x2 1/8 pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f clk f xt f xx f x f r /8 f r frc bit subclock oscillator xt1 xt2 f xt interval timer brg f brg = f x /2 to f x /2 12 idle mode watch timer clock watch timer clock, watchdog timer 2 clock cls bit, ck3 bit halt control halt mode cpu clock f cpu peripheral clock watchdog timer 1 clock watchdog timer 2 clock internal system clock f xx to f xx /1024 f xw selector selector selector selector ck2 to ck0 bits idle mode idle mode idle control idle control idle control prescaler 2 prescaler 1 main clock stop detection mck bit pllon bit selpll bit stop mode main clock oscillator main clock oscillator stop control mfrc bit port cm f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f brg : watch timer clock frequency f xw : watchdog timer 1 clock frequency f r : ring-osc clock frequency chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 173 (1) main clock oscillator the main clock oscillator oscillates the following frequencies (f x ). ? f x = 2 mhz (regc = v dd = 2.7 to 5.5 v, in pll mode) ? f x = 2 to 5 mhz (regc = v dd = 4.5 to 5.5 v, in pll mode) ? f x = 2 to 8 note mhz (regc = v dd = 2.7 to 5.5 v, in clock-through mode) note this value may change after evaluation. (2) subclock oscillator the subclock oscillator oscillat es a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscill ator is stopped in the st op mode or when the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) prescaler 1 this prescaler generates the clock (f xx to f xx /1024) to be supplied to the following on-chip peripheral functions: tmp0, tm00, tm01, tm50, tm51, tmh0, tmh1, csi00, csi01, csia0, uart0, uart1, i 2 c0, and adc (5) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom correction, rom, and ram blocks, and can be output from the clkout pin. (6) interval timer brg this circuit divides the clock (f x ) generated by the main clock oscillator to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. it can also be used as an interval timer. for details, refer to chapter 11 interval timer, watch timer . (7) pll this circuit multiplies the clock (f x ) generated by the main clock oscillator. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be sele cted by using the pllctl.selpll bit. operation of the pll c an be started or stopped by the pllctl.pllon bit. (8) ring-osc (on-chip ring oscillator) the ring-osc oscillator oscillates a frequency (f r ) of 120 to 480 khz (240 khz (typ.)). chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 174 6.3 registers (1) processor clock control register (pcc) the pcc register is a special register. data can be wr itten to this register only in combination of specific sequences (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. after reset, pcc is set to 03h. (1/2) frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 control of main clock oscillator used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. < > < > < > note the cls bit is a read-only bit. chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 175 (2/2) f xx f xx /2 f xx /4 f xx /8 (default value) f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. 3. when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wa it occurs using an access met hod that causes a wait (refer to 3.4.8 (2) access to special on-chip peripheral i/o regist er for details of the access methods). if a wait occurs, it can only be released by a reset. remark : don?t care chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 176 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instructi on is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if subclock operation has started. it takes the following time after the ck3 bit is se t until subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping th e main clock, stop the pll. 2. if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. main clock (f xx ) > subclock (f xt : 32.768 khz) 4 [description example] <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped remark the above description is an exampl e. note with caution that t he cls bit is read in a closed loop in <2>. chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 177 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock starts oscillating <2> insert waits by the program and wait until the oscillation stabilizat ion time of the main clock elapses. <3> ck3 bit 0: use of a bit manipulation instruct ion is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time after the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one nop instructi on immediately after setting the ck3 bit to 0 or read the cls bit to check if main clock operation has started. [description example] <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time _wait_ost : nop nop nop addi -1, r11, r11 mp r0, r11 bne _program_wait <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts bnz _check_cls remark the above description is an exampl e. note with caution that t he cls bit is read in a closed loop in <4>. chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 178 (2) ring-osc mode register (rcm) the rcm register is an 8-bit register that se ts the operation mode of the ring-osc oscillator. this register can be read or written in 8-bit or 1-bit units. after reset, rcm is cleared to 00h. caution the settings of the rcm register differ fo r a mask rom version and flash memory version. refer to chapter 28 mask opt ion/option byte for details. ? mask rom version ( pd703308, 703308y) valid when ?(ring-osc) can be stopped by software? is selected by the mask option. ? flash memory version ( pd70f3306, 70f3306y, 70f3308, 70f3308y) valid when ringstp is cleared to 0 by the option byte setting. 0 rcm 0 0 0 0 0 0 rstop after reset: 00h r/w address: fffff80ch < > ring-osc oscillation enabled. ring-osc oscillation disabled (stopped). rstop 0 1 enables/disables ring-osc oscillation (3) cpu operation clock status register (ccls) the ccls register indicates the cpu operation clock status. this register is read-only, in 8-bit or 1-bit units. after reset, ccls is cleared to 00h. 0 ccls 0 0 0 0 0 0 cclsf after reset: 00h r address: fffff82eh operates on main clock (f x ) or subclock (f xt ). operates on ring-osc (f r ). cclsf 0 1 cpu operation clock status chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 179 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register cls bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) { { { { { subclock oscillator (f xt ) { { { { { { { { { cpu clock (f cpu ) { { internal system clock (f clk ) { { { peripheral clock (f xx to f xx /1024) { { wt clock (main) { { { { { wt clock (sub) { { { { { { { { { wdt1 clock (f xw ) { { { { { wdt2 clock (ring-osc) { { { { { { { { wdt2 clock (sub) { { { { { { { { { remark o: operable : stopped 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alte rnately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clko ut pin is the same as the in ternal system clock in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped status. however, the port mode (pcm1: input mode) is selected until the clkout pin output is set after reset. cons equently, the clkout pin goes into a high-impedance state. 6.4.3 external clock input function an external clock can be direct ly input to the oscillator. input the clock to the x1 pin and its inverse signal to the x2 pin. set the pcc.mfrc bit to 1 (on-chip feedback resistor not used). note, however, that oscillation stabilization time is inserted even in the external clock mode. connect v dd directly to the regc pin. chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 180 6.5 pll function 6.5.1 overview the pll function is used to output the operating clock of the cpu and per ipheral macro at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. when pll function is used: input clock = 2 to 5 mhz (f xx : 8 to 20 mhz) clock-through mode: input clock = 2 to 10 mhz (f xx : 2 to 10 mhz) 6.5.2 register (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the security function of pll and rto. this register can be read or written in 8-bit or 1-bit units. after reset, pllctl is set to 01h. 0 pllctl 0 0 0 0 rtost0 note selpll pllon pll stopped pll operating pllon 0 1 pll operation stop register clock-through operation pll operation selpll 0 1 pll clock selection register after reset: 01h r/w address: fffff806h < > < > < > note for the rtost0 bit, refer to chapter 13 real-time output function (rto) . caution be sure to clear bits 4 to 7 to 0. chan ging bit 3 does not a ffect the operation. chapter 6 clock generation function preliminary user?s manual u16895ej1v0ud 181 6.5.3 usage (1) when pll is used ? after reset has been released, the pll operates (pll ctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bit = 0), select the pll mode (selpll bit = 1). ? to set the stop mode in which the main clock is stoppe d, or to set the idle mode, first select the clock- through mode and then stop the pll. to return from the idle or stop mode, first enable pll operation (pllon bit = 1), and then select the pll mode (selpll bit = 1). ? to enable the pll operation, first se t the pllon bit to 1, wait for 200 s, and then set the selpll bit to 1. to stop the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). (2) when pll is not used ? the clock-through mode (selpll bit = 0) is select ed after reset has been released, but the pll is operating (pllon bit = 1) and must t herefore be stopped (pllon bit = 0). remark the pll is operable in the idle mode. to realiz e low power consumption, stop the pll. be sure to stop the pll when shifting to the stop mode. preliminary user?s manual u16895ej1v0ud 182 chapter 7 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850es/kf1+ incorporates tmp0. 7.1 overview an outline of tmp0 is shown below. ? clock selection: 8 ways ? capture trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 7.2 functions tmp0 has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 183 7.3 configuration tmp0 includes the following hardware. table 7-1. configuration of tmp0 item configuration timer register 16-bit counter registers tmp0 capture/compare registers 0, 1 (tp0ccr0, tp0ccr1) tmp0 counter read buffer register (tp0cnt) ccr0, ccr1 buffer registers timer inputs 2 (tip00 note , tip01 pins) timer outputs 2 (top00, top01 pins) control registers tmp0 control registers 0, 1 (tp0ctl0, tp0ctl1) tmp0 i/o control registers 0 to 2 (tp0ioc0 to tp0ioc2) tmp0 option registers 0, 1 (tp0opt0, tp0opt1) note the tip00 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. figure 7-1. block diagram of tmp0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 selector internal bus internal bus top00 top01 tip00 tip01 selector ccr0 buffer register ccr1 buffer register tp0ccr0 tp0ccr1 16-bit counter tp0cnt inttp0ov inttp0cc0 inttp0cc1 output controller clear edge detector edge detector digital noise eliminator remark f xx : main clock frequency chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 184 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tp0cnt register. when the tp0ctl0.tp0ce bit = 0, the va lue of the 16-bit counter is ffffh. if the tp0cnt register is read at this time, 0000h is read. reset input clears the tp0ce bit to 0. t herefore, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tp0ccr0 register is used as a compare regist er, the value written to the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttp0cc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tp0ccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tp0ccr1 register is used as a compare regist er, the value written to the tp0ccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttp0cc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tp0ccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tip00 and tip01 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tp0ioc1 and tp0ioc2 registers. (5) output controller this circuit controls the output of the top00 and top0 1 pins. the output contro ller is controlled by the tp0ioc0 register. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. (7) digital noise eliminator this circuit is valid only when the tip00 and tip 01 pins are used as a capture trigger input pin. this circuit is controlled by the p0nfc and p1nfc registers. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 185 7.4 registers (1) tmp0 control re gister 0 (tp0ctl0) the tp0ctl0 register is an 8-bit register that controls the operation of tmp0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tp0ctl0 register by software. tp0ce tmp0 operation disabled (tmp0 reset asynchronously note ). tmp0 operation enabled. tmp0 operation started. tp0ce 0 1 tmp0 operation control tp0ctl0 0 0 0 0 tp0cks2 tp0cks1 tp0cks0 654321 after reset: 00h r/w address: fffff5a0h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tp0cks2 0 0 0 0 1 1 1 1 internal count clock selection tp0cks1 0 0 1 1 0 0 1 1 tp0cks0 0 1 0 1 0 1 0 1 note tp0opt0.tp0ovf bit, 16-bit counter , timer output (top00, top01 pins) cautions 1. set the tp0cks2 to tp0 cks0 bits when the tp0ce bit = 0. when the value of the tp0ce bi t is changed from 0 to 1, the tp0cks2 to tp0cks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to 0. remark f xx : main clock frequency chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 186 (2) tmp0 control re gister 1 (tp0ctl1) the tp0ctl1 register is an 8-bit register that controls the operation of tmp0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tp0est 0 1 software trigger control tp0ctl1 tp0est tp0eee 0 0 tp0md2 tp0md1 tp0md0 <6> <5> 4 3 2 1 after reset: 00h r/w address: fffff5a1h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tp0est bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tp0est bit as the trigger. disable operation with external event count input. (perform counting with the count clock selected by the tp0ctl0.tp0ck0 to tp0ctl0.tp0ck2 bits.) tp0eee 0 1 count clock selection the tp0eee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tp0md2 0 0 0 0 1 1 1 1 timer mode selection tp0md1 0 0 1 1 0 0 1 1 tp0md0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) ? cautions 1. the tp0est bit is valid only in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tp0eee bit. 3. set the tp0eee and tp0md2 to tp0md0 bits when the tp0ctl0.tp0ce bit = 0. (the sam e value can be written when the tp0ce bit = 1.) the operation is not guaranteed when rewriting is performed with the tp0ce bit = 1. if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to 0. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 187 (3) tmp0 i/o control register 0 (tp0ioc0) the tp0ioc0 register is an 8-bit register that controls the timer output (top00, top01 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tp0ol1 0 1 top01 pin output level setting top01 pin output inversion disabled top01 pin output inversion enabled tp0ioc0 0 0 0 tp0ol1 tp0oe1 tp0ol0 tp0oe0 6543<2>1 after reset: 00h r/w address: fffff5a2h tp0oe1 0 1 top01 pin output setting timer output disabled ? when tp0ol1 bit = 0: low level is output from the top01 pin ? when tp0ol1 bit = 1: high level is output from the top01 pin tp0ol0 0 1 top00 pin output level setting top00 pin output inversion disabled top00 pin output inversion enabled tp0oe0 0 1 top00 pin output setting timer output disabled ? when tp0ol0 bit = 0: low level is output from the top00 pin ? when tp0ol0 bit = 1: high level is output from the top00 pin 7 <0> timer output enabled (a square wave is output from the top01 pin). timer output enabled (a square wave is output from the top00 pin). cautions 1. rewrite the tp0ol1, tp0oe1, tp0ol0, and tp0oe0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. even if the tp0ola bit is manipulated when the tp0ce and tp0oea bits are 0, the top0a pin output level varies (a = 0, 1). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 188 (4) tmp0 i/o control register 1 (tp0ioc1) the tp0ioc1 register is an 8-bit regist er that controls the valid edge of the capture trig ger input signals (tip00, tip01 pins). this register can be read or written in 8-bit units. reset input clears this register to 00h. 0 tp0is3 0 0 1 1 tp0is2 0 1 0 1 capture trigger input signal (tip01 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tp0ioc1 0 0 0 tp0is3 tp0is2 tp0is1 tp0is0 654321 after reset: 00h r/w address: fffff5a3h tp0is1 0 0 1 1 tp0is0 0 1 0 1 capture trigger input signal (tip00 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tp0is3 to tp0is0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. the tp0is3 to tp0is0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 189 (5) tmp0 i/o control register 2 (tp0ioc2) the tp0ioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tip00 pin) and external trigger input signal (tip00 pin). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tp0ees1 0 0 1 1 tp0ees0 0 1 0 1 external event count input signal (tip00 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tp0ioc2 0 0 0 tp0ees1 tp0ees0 tp0ets1 tp0ets0 654321 after reset: 00h r/w address: fffff5a4h tp0ets1 0 0 1 1 tp0ets0 0 1 0 1 external trigger input signal (tip00 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tp0ees1, tp0ees0, tp0ets1, and tp0ets0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. the tp0ees1 and tp0ees0 bi ts are valid only when the tp0ctl1.tp0eee bit = 1 or when the external event count mode (tp0ctl1.tp0md2 to tp0ctl1.tp0md0 bits = 001) has been set. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 190 (6) tmp0 option register 0 (tp0opt0) the tp0opt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tp0ccs1 0 1 tp0ccr1 register capture/compare selection the tp0ccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tp0opt0 0 tp0ccs1 tp0ccs0 0 0 0 tp0ovf 654321 after reset: 00h r/w address: fffff5a5h tp0ccs0 0 1 tp0ccr0 register capture/compare selection the tp0ccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tp0ovf set (1) reset (0) tmp0 overflow detection flag the tp0ovf bit is reset when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. an interrupt request signal (inttp0ov) is generated at the same time that the tp0ovf bit is set to 1. the inttp0ov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. the tp0ovf bit is not cleared even when the tp0ovf bit or the tp0opt0 register are read when the tp0ovf bit = 1. the tp0ovf bit can be both read and written, but the tp0ovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmp0. overflow occurred tp0ovf bit 0 written or tp0ctl0.tp0ce bit = 0 7 <0> cautions 1. rewrite the tp0ccs1 and tp0ccs0 bits when the tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mi stakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to 0. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 191 (7) tmp0 capture/compare register 0 (tp0ccr0) the tp0ccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tp0opt0.tp0ccs0 bit. in the pulse width measurement mode, the tp0ccr0 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tp0ccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tp0ccr0 register is disable d during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff5a6h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 192 (a) function as compare register the tp0ccr0 register can be rewritten even when the tp0ctl0.tp0ce bit = 1. the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttp0cc0) is generated. if top00 pin output is ena bled at this time, the output of the top00 pin is inverted. when the tp0ccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. (b) function as capture register when the tp0ccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tp0ccr0 register if the valid ed ge of the capture trigger input pin (tip00 pin) is detected. in the pulse width measur ement mode, the count value of the 16-bit counter is stored in the tp0ccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tip00 pin) is detected. even if the capture operation and reading the tp0 ccr0 register conflict, the correct value of the tp0ccr0 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 193 (8) tmp0 capture/compare register 1 (tp0ccr1) the tp0ccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tp0opt0.tp0ccs1 bit. in the pulse width measurement mode, the tp0ccr1 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tp0ccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tp0ccr1 register is disable d during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff5a8h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 194 (a) function as compare register the tp0ccr1 register can be rewritten even when the tp0ctl0.tp0ce bit = 1. the set value of the tp0ccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttp0cc1) is generated. if top01 pin output is ena bled at this time, the output of the top01 pin is inverted. (b) function as capture register when the tp0ccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tp0ccr1 register if the valid ed ge of the capture trigger input pin (tip01 pin) is detected. in the pulse width measur ement mode, the count value of the 16-bit counter is stored in the tp0ccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tip01 pin) is detected. even if the capture operation and reading the tp0 ccr1 register conflict, the correct value of the tp0ccr1 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 195 (9) tmp0 counter read buffer register (tp0cnt) the tp0cnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tp0ctl0.tp0ce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tp0cnt register is cleared to 0000h when the tp0ce bit = 0. if the tp0cnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tp0cnt register is cleared to 000 0h after reset, as the tp0ce bit is cleared to 0. caution accessing the tp0cnt register is disabl ed during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff5aah 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 196 7.5 operation tmp0 can perform the following operations. operation tp0ctl1.tp0est bit (software trigger bit) tip00 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that t he valid edge of the tip00 pin capture trigger input is not detected (by clearing the tp0ioc1.tp0i s1 and tp0ioc1.tp0is0 bits to ?00?). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tp0ctl1.tp0eee bit to 0). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 197 7.5.1 interval timer mode (t p0md2 to tp0md0 bits = 000) in the interval timer mode, an interrupt request signal (inttp0cc0) is generated at t he specified interval if the tp0ctl0.tp0ce bit is set to 1. a square wave whose half cycle is equal to the interval can be output from the top00 pin. usually, the tp0ccr1 register is not used in the interval timer mode. figure 7-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tp0ce bit tp0ccr0 register count clock selection clear match signal top00 pin inttp0cc0 signal figure 7-3. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 198 when the tp0ce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the top00 pin is inverted. additionally, the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, the output of the top00 pin is in verted, and a compare match interrupt request signal (inttp0cc0) is generated. the interval can be calculated by the following expression. interval = (set value of tp0ccr0 register + 1) count clock cycle figure 7-4. register setting for in terval timer mode operation (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce (b) tmp0 control register 1 (tp0ctl1) 00000 tp0ctl1 0, 0, 0: interval timer mode 000 tp0md2 tp0md1 tp0md0 tp0eee tp0est (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level with operation of top00 pin disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 199 figure 7-4. register setting for in terval timer mode operation (2/2) (d) tmp0 counter read buffer register (tp0cnt) by reading the tp0cnt register, the count va lue of the 16-bit counter can be read. (e) tmp0 capture/compare register 0 (tp0ccr0) if the tp0ccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmp0 capture/compare register 1 (tp0ccr1) usually, the tp0ccr1 register is not used in the inte rval timer mode. however, the set value of the tp0ccr1 register is transferred to the ccr1 buffer register. a compare match interrupt request signal (inttp0cc1) is generated when the count value of th e 16-bit counter matches the value of the ccr1 buffer register. therefore, mask the interrupt request by using the corresponding interrupt mask flag (tp0ccmk1). remark tmp0 i/o control register 1 (tp0ioc1), tm p0 i/o control register 2 (tp0ioc2), and tmp0 option register 0 (tp0opt0) are not used in the interval timer mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 200 (1) interval timer mode operation flow figure 7-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ccr0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 201 (2) interval timer mode operation timing (a) operation if tp0ccr0 register is cleared to 0000h if the tp0ccr0 register is cleared to 0000h, the inttp 0cc0 signal is generated at each count clock, and the output of the top00 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 202 (b) operation if tp0ccr0 register is set to ffffh if the tp0ccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. t he counter is cleared to 0000h in synchronization with the next count-up timing. the inttp0cc0 signal is generated and the output of the top00 pin is inverted. at this time, an overflow interrupt request signal (inttp0ov) is not generated, nor is the overflow flag (tp0opt0.tp0ovf bit) set to 1. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 203 (c) notes on rewriting tp0ccr0 register to change the value of the tp0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tp0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register tp0ol0 bit top00 pin output inttp0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remark interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle if the value of the tp0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tp0ccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttp0cc0 signal is generated and the output of the top00 pin is inverted. therefore, the inttp0cc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock cycle?. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 204 (d) operation of tp0ccr1 register figure 7-6. configuration of tp0ccr1 register ccr0 buffer register tp0ccr0 register tp0ccr1 register ccr1 buffer register top00 pin inttp0cc0 signal top01 pin inttp0cc1 signal 16-bit counter output controller tp0ce bit count clock selection clear match signal output controller match signal chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 205 if the set value of the tp0ccr1 register is less than the set value of the tp0ccr0 register, the inttp0cc1 signal is generated once per cycle. at the same time, the output of the top01 pin is inverted. the top01 pin outputs a square wave with the sa me cycle as that output by the top00 pin. figure 7-7. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 206 if the set value of the tp0ccr1 register is greater than the set value of the tp0ccr0 register, the count value of the 16-bit counter does not match the va lue of the tp0ccr1 register. consequently, the inttp0cc1 signal is not generated, nor is the output of the top01 pin changed. figure 7-8. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 207 7.5.2 external event count mode (tp0md2 to tp0md0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tp0ctl0.tp0ce bit is set to 1, and an interrupt request si gnal (inttp0cc0) is generated each time the specified number of edges have been counted . the top00 pin cannot be used. usually, the tp0ccr1 register is not us ed in the external event count mode. figure 7-9. configuration in external event count mode 16-bit counter ccr0 buffer register tp0ce bit tp0ccr0 register edge detector clear match signal inttp0cc0 signal tip00 pin (external event count input) figure 7-10. basic timing in external event count mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 0 d 0 d 0 d 0 16-bit counter tp0ccr0 register inttp0cc0 signal external event count input (tip00 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) remark this figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 208 when the tp0ce bit is set to 1, the value of the 16-bit counter is clea red from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttp0cc0) is generated. the inttp0cc0 signal is generated each time the valid e dge of the external event count input has been detected (set value of tp0ccr0 register + 1) times. figure 7-11. register setting for operati on in external event count mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 0: stop counting 1: enable counting 000 tp0cks2 tp0cks1 tp0cks0 tp0ce (b) tmp0 control register 1 (tp0ctl1) 00000 tp0ctl1 0, 0, 1: external event count mode 001 tp0md2 tp0md1 tp0md0 tp0eee tp0est (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0 0 tp0oe1 tp0ol0 tp0oe0 tp0ol1 (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 209 figure 7-11. register setting for operati on in external event count mode (2/2) (e) tmp0 counter read buffer register (tp0cnt) the count value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register 0 (tp0ccr0) if d 0 is set to the tp0ccr0 register, the counter is cleared and a compare match interrupt request signal (inttp0cc0) is generated when the nu mber of external event counts reaches (d 0 + 1). (g) tmp0 capture/compare register 1 (tp0ccr1) usually, the tp0ccr1 register is not used in the exte rnal event count mode. however, the set value of the tp0ccr1 register is transferred to the ccr1 buff er register. when the count value of the 16-bit counter matches the value of the ccr1 buffer regi ster, a compare match interrupt request signal (inttp0cc1) is generated. therefore, mask the interrupt signal by using the interrupt mask flag (tp0ccmk1). remark tmp0 i/o control register 1 (tp0ioc1) and tmp0 option register 0 (tp0opt0) are not used in the external event count mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 210 (1) external event count mode operation flow figure 7-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 211 (2) operation timing in external event count mode (a) operation if tp0ccr0 register is cleared to 0000h if the tp0ccr0 register is cleared to 0000h, the in ttp0cc0 signal is generated each time the valid signal of the external event count signal has been detected. the 16-bit counter is always 0000h. external event count signal 16-bit counter tp0ce bit tp0ccr0 register inttp0cc0 signal 0000h external event count signal interval external event count signal interval external event count signal interval ffffh 0000h 0000h 0000h 0000h (b) operation if tp0ccr0 register is set to ffffh if the tp0ccr0 register is set to ffffh, the 16-bit co unter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttp0cc0 signal is generated. at this time, the tp0opt0.tp0ovf bit is not set. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 212 (c) notes on rewriting the tp0ccr0 register to change the value of the tp0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tp0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) if the value of the tp0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tp0ccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttp0cc0 signal is generated. therefore, the inttp0cc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 213 (d) operation of tp0ccr1 register figure 7-13. configuration of tp0ccr1 register ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller top01 pin inttp0cc1 signal edge detector tip00 pin if the set value of the tp0ccr1 register is smalle r than the set value of the tp0ccr0 register, the inttp0cc1 signal is generated once per cycle. at the same time, the output signal of the top01 pin is inverted. figure 7-14. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 214 if the set value of the tp0ccr1 register is greater than the set value of the tp0ccr0 register, the inttp0cc1 signal is not generated because the count va lue of the 16-bit counte r and the value of the tp0ccr1 register do not match. nor is t he output signal of t he top01 pin changed. figure 7-15. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 215 7.5.3 external trigger pulse output m ode (tp0md2 to tp0md0 bits = 010) in the external trigger pulse output mode, 16-bit timer/event counter p waits for a trigger when the tp0ctl0.tp0ce bit is set to 1. when the valid edge of an ex ternal trigger input signal is detected, 16-bit timer/event counter p starts counting, and outputs a pwm waveform from the top01 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the top00 pin. figure 7-16. configuration in external trigger pulse output mode ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) output controller top01 pin inttp0cc1 signal top00 pin count clock selection count start control edge detector software trigger generation tip00 pin transfer transfer s r chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 216 figure 7-17. basic timing in exte rnal trigger pulse output mode external trigger input (tip00 pin input) top00 pin output (software trigger) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output 16-bit timer/event counter p waits for a trigger when the tp0c e bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the top01 pin. if the trigger is generated again while the counter is opera ting, the counter is cleared to 0000h and restarted. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tp0ccr1 register) count clock cycle cycle = (set value of tp0ccr0 register + 1) count clock cycle duty factor = (set value of tp0ccr1 regist er)/(set value of tp0ccr0 register + 1) the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tp0ccra register is transferred to t he ccra buffer register when the count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal, or setting the software trigger (tp0ctl1.tp0est bit) to 1 is used as the trigger. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 217 figure 7-18. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0/1 0/1 0 0 tp0ctl1 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count with external event input signal generate software trigger when 1 is written 010 tp0md2 tp0md1 tp0md0 tp0eee tp0est 0, 1, 0: external trigger pulse output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output settings of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 218 figure 7-18. setting of registers in exte rnal trigger pulse output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the external trigger pulse output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 219 (1) operation flow in extern al trigger pulse output mode figure 7-19. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) top00 pin output (software trigger) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 220 figure 7-19. software processing flow in ex ternal trigger pulse output mode (2/2) tp0ce bit = 1 setting of tp0ccr0 register register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting is enabled (tp0ce bit = 1). trigger wait status tp0ccr1 register write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. start setting of tp0ccr1 register <1> count operation start flow <2> tp0ccr0 and tp0ccr1 register setting change flow setting of tp0ccr0 register when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. setting of tp0ccr1 register <4> tp0ccr0, tp0ccr1 register setting change flow only writing of the tp0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. setting of tp0ccr1 register <3> tp0ccr0, tp0ccr1 register setting change flow tp0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 221 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tp0ccr1 register last. rewrite the tp0ccra register after writing the tp0ccr1 register after the inttp0cc0 signal is detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) top00 pin output (software trigger) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 222 in order to transfer data from the tp0ccra register to the ccra buffer register, the tp0ccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tp0ccr0 register and then set the active level width to the tp0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tp0ccr0 register, and then write the same value to the tp0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tp0ccr1 register has to be set. after data is written to the tp0ccr1 register, the val ue written to the tp0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tp0ccr0 or tp0ccr1 register again after writing the tp0ccr1 register once, do so after the inttp0cc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tp0ccr a register to the ccra bu ffer register conflicts with writing the tp0ccra register. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 223 (b) 0%/100% output of pwm waveform to output a 0% waveform, clear the tp0ccr1 register to 0000h. if the set value of the tp0ccr0 register is ffffh, the inttp0cc1 signal is generated periodically. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 to output a 100% waveform, set a value of (set value of tp0ccr0 register + 1) to the tp0ccr1 register. if the set value of the tp0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 224 (c) conflict between trigger detecti on and match with tp0ccr1 register if the trigger is detected immediately after the inttp 0cc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the top01 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened if the trigger is detected immediately before the inttp 0cc1 signal is generated, the inttp0cc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. t he output signal of the top01 pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 225 (d) conflict between trigger detecti on and match with tp0ccr0 register if the trigger is detected immediately after the inttp 0cc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the top01 pin is extended by time from generation of the inttp0cc0 signal to trigger detection. 16-bit counter tp0ccr0 register inttp0cc0 signal top01 pin output external trigger input (tip00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended if the trigger is detected immediately before the inttp 0cc0 signal is generated, the inttp0cc0 signal is not generated. the 16-bit counter is cleared to 0000h, the top01 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter tp0ccr0 register inttp0cc0 signal top01 pin output external trigger input (tip00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 226 (e) generation timing of compare match interrupt request signal (inttp0cc1) the timing of generation of the inttp0cc1 signal in the external trigger pulse output mode differs from the timing of other inttp0cc1 signals; the inttp0cc1 signal is generated when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated in synch ronization with the next count up, after the count value of the 16-bit counter matches the value of the tp0ccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the top01 pin. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 227 7.5.4 one-shot pulse output mode (tp0md2 to tp0md0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter p waits for a trigger when the tp0ctl0.tp0ce bit is set to 1. when the valid edge of an external trigger input is detected, 16-bit timer/event counter p starts counting, and outputs a one-shot pulse from the top01 pin. instead of the external trigger, a software trigger can also be generated to output the pulse. when the software trigger is used, the top00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 7-20. configuration in one-shot pulse output mode ccr0 buffer register tp0ce bit tp0ccr0 register tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) top01 pin inttp0cc1 signal top00 pin count clock selection count start control edge detector software trigger generation tip00 pin transfer transfer s r output controller (rs-ff) s r 16-bit counter chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 228 figure 7-21. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 0 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) top00 pin output (software trigger) when the tp0ce bit is set to 1, 16-bit timer/event counter p waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng, and outputs a one-shot pul se from the top01 pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one-s hot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tp0ccr1 register) count clock cycle active level width = (set value of tp0ccr0 register ? set value of tp0ccr1 register + 1) count clock cycle the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts after its count value matches the value of the c cr0 buffer register. the compare match interrupt request signal inttp0cc1 is generated when the count value of the 16-bit counter matches the va lue of the ccr1 buffer register. the valid edge of an external trigger input or setting the so ftware trigger (tp0ctl1.tp0est bit) to 1 is used as the trigger. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 229 figure 7-22. setting of registers in one-shot pulse output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0/1 0/1 0 0 tp0ctl1 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tp0md2 tp0md1 tp0md0 tp0eee tp0est 0, 1, 1: one-shot pulse output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 230 figure 7-22. setting of registers in one-shot pulse output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 1 ? d 0 + 1) count clock cycle output delay period = d 1 count clock cycle remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the one-shot pulse output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 231 (1) operation flow in one-shot pulse output mode figure 7-23. software processing flow in one-shot pulse output mode <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). trigger wait status count operation is stopped start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 0 d 0 d 1 d 1 d 0 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 232 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tp0ccra register to change the set value of the tp0ccra register to a smaller value, stop counting once, and then change the set value. if the value of the tp0ccra register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) top00 pin output (software trigger) when the tp0ccr0 register is rewritten from d 00 to d 01 and the tp0ccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tp0ccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tp0ccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter count s up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttp0cc1 signal and asserts the top01 pin. when the count value matches d 01 , the counter generates the in ttp0cc0 signal, deasserts the top01 pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 233 (b) generation timing of compare match interrupt request signal (inttp0cc1) the generation timing of the inttp0cc1 signal in the one-shot pulse output mode is different from other inttp0cc1 signals; the inttp0cc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated when the 16- bit counter counts up next time after its count value matches the value of the tp0ccr1 register. in the one-shot pulse output mode, howe ver, it is generated one clock earlier. this is because the timing is changed to match the change timing of the top01 pin. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 234 7.5.5 pwm output mode (tp0md 2 to tp0md0 bits = 100) in the pwm output mode, a pwm waveform is output from the top01 pin when the tp0ctl0.tp0ce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the top00 pin. figure 7-24. configuration in pwm output mode ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) output controller top01 pin inttp0cc1 signal top00 pin count clock selection count start control transfer transfer s r chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 235 figure 7-25. basic timing in pwm output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal top00 pin output tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 ? d 10 + 1) when the tp0ce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a pwm waveform from the top01 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tp0ccr1 register ) count clock cycle cycle = (set value of tp0ccr0 register + 1) count clock cycle duty factor = (set value of tp0ccr1 regist er)/(set value of tp0ccr0 register + 1) the pwm waveform can be changed by rewriting the tp0ccra register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tp0ccra register is transferred to t he ccra buffer register when the count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 236 figure 7-26. register setting in pwm output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 00000 tp0ctl1 100 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 0, 0: pwm output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 237 figure 7-26. register setting in pwm output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input. 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the pwm output mode. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 238 (1) operation flow in pwm output mode figure 7-27. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal top00 pin output tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> <3> <4> <5> <1> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 239 figure 7-27. software processing flow in pwm output mode (2/2) tp0ce bit = 1 setting of tp0ccr0 register register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting is enabled (tp0ce bit = 1). tp0ccr1 write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. start setting of tp0ccr1 register <1> count operation start flow <2> tp0ccr0, tp0ccr1 register setting change flow setting of tp0ccr0 register when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tp0ccr1 register <4> tp0ccr0, tp0ccr1 register setting change flow only writing of the tp0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tp0ccr1 register <3> tp0ccr0, tp0ccr1 register setting change flow tp0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 240 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tp0ccr1 register last. rewrite the tp0ccra register after writing the tp0ccr1 register after the inttp0cc1 signal is detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register tp0ccr1 register ccr1 buffer register top01 pin output inttp0cc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tp0ccra register to the ccr a buffer register, the tp0ccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tp0ccr0 register and then set the active level to the tp0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tp0ccr0 register, and then write the same value to the tp0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tp0ccr1 register has to be set. after data is written to the tp0ccr1 register, the val ue written to the tp0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tp0ccr0 or tp0ccr1 register again after writing the tp0ccr1 register once, do so after the inttp0cc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tp0ccr a register to the ccra bu ffer register conflicts with writing the tp0ccra register. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 241 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tp0ccr1 register to 0000h. if the set value of the tp0ccr0 register is ffffh, the inttp0cc1 signal is generated periodically. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 to output a 100% waveform, set a value of (set value of tp0ccr0 register + 1) to the tp0ccr1 register. if the set value of the tp0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 242 (c) generation timing of compare match interrupt request signal (inttp0cc1) the timing of generation of the inttp0cc1 signal in the pwm output mode differs from the timing of other inttp0cc1 signals; the inttp0cc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the tp0ccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the top01 pin. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 243 7.5.6 free-running timer mode (t p0md2 to tp0md0 bits = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tp0ctl0.tp0ce bit is set to 1. at this time, the tp0ccra register can be used as a compare register or a c apture register, depending on the setting of the tp0opt0.tp0ccs 0 and tp0opt0.tp0ccs1 bits. figure 7-28. configuration in free-running timer mode tp0ccr0 register (capture) tp0ce bit tp0ccr1 register (capture) 16-bit counter tp0ccr1 register (compare) tp0ccr0 register (compare) output controller tp0ccs0, tp0ccs1 bits (capture/compare selection) top00 pin output output controller top01 pin output edge detector count clock selection digital noise eliminator digital noise eliminator tip00 pin (external event count input/ capture trigger input) tip01 pin (capture trigger input) internal count clock 0 1 0 1 inttp0ov signal inttp0cc1 signal inttp0cc0 signal edge detector edge detector remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 244 when the tp0ce bit is set to 1, 16-bit timer/event counter p starts counting, and the output signals of the top00 and top01 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tp0ccra register, a compare match interrupt request signal (inttp0 cca) is generated, and the out put signal of the top0a pin is inverted. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttp0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tp0opt0.tp0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tp0ccra register can be rewritten whil e the counter is operating. if it is re written, the new value is reflected at that time, and compared with the count value. figure 7-29. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 245 when the tp0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tip0a pin is detected, the count value of the 16-bit counter is stored in the tp0ccra register, and a capture interrupt request signal (inttp0cca) is generated. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttp0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tp0opt0.tp0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 7-30. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 246 figure 7-31. register setting in free-running timer mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1 (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 101 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 0, 1: free-running mode 0: operate with count clock selected by tp0cks0 to tp0cks2 bits 1: count on external event count input signal (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level with operation of top00 pin disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 247 figure 7-31. register setting in free-running timer mode (2/2) (d) tmp0 i/o control register 1 (tp0ioc1) 0 0 0 0 0/1 tp0ioc1 select valid edge of tip00 pin input select valid edge of tip01 pin input 0/1 0/1 0/1 tp0is2 tp0is1 tp0is0 tp0is3 (e) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (f) tmp0 option register 0 (tp0opt0) 0 0 0/1 0/1 0 tp0opt0 overflow flag specifies if tp0ccr0 register functions as capture or compare register specifies if tp0ccr1 register functions as capture or compare register 0 0 0/1 tp0ccs0 tp0ovf tp0ccs1 (g) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (h) tmp0 capture/compare regist ers 0 and 1 (tp0ccr0 and tp0ccr1) these registers function as captur e registers or compare registers depending on the setting of the tp0opt0.tp0ccsa bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to t he tip0a pin is detected. when the registers function as compare registers and when d a is set to the tp0ccra register, the inttp0cca signal is generated when the counter reaches (d a + 1), and the output signal of the top0a pin is inverted. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 248 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 7-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 249 figure 7-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tp0ce bit = 1 read tp0opt0 register (check overflow flag). register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0opt0 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). start execute instruction to clear tp0ovf bit (clr tp0ovf). <1> count operation start flow <2> overflow flag clear flow tp0ce bit = 0 counter is initialized and counting is stopped by clearing tp0ce bit to 0. stop <3> count operation stop flow tp0ovf bit = 1 no yes chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 250 (b) when using capture/compare register as capture register figure 7-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 251 figure 7-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tp0ce bit = 1 read tp0opt0 register (check overflow flag). register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc1 register, tp0opt0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). start execute instruction to clear tp0ovf bit (clr tp0ovf). <1> count operation start flow <2> overflow flag clear flow tp0ce bit = 0 counter is initialized and counting is stopped by clearing tp0ce bit to 0. stop <3> count operation stop flow tp0ovf bit = 1 no yes chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 252 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an interval timer with the tp0ccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttp0cca signal has been detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the corresponding tp0ccra register must be re-set in the interrupt servicing that is executed when the inttp0cca signal is detected. the set value for re-setting the tp0ccra register can be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 253 (b) pulse width measurement with capture register when pulse width measurement is performed with the tp0ccra register used as a capture register, software processing is necessary for reading the capt ure register each time the inttp0cca signal has been detected and for calculating an interval. ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the fr ee-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calcul ated by reading the value of the tp0ccra register in synchronization with the inttp0cca signal, and calc ulating the difference between the read value and the previously read value. remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 254 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register tip01 pin input tp0ccr1 register inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> read the tp0ccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tp0ccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 255 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tp0ce bit inttp0ov signal tp0ovf bit tp0ovf0 flag note tip00 pin input tp0ccr0 register tp0ovf1 flag note tip01 pin input tp0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tp0ovf0 and tp0ovf1 flags are set on the internal ram by software. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> an overflow occurs. set the tp0ovf0 and tp0ovf 1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tp0ccr0 register. read the tp0ovf0 flag. if the tp0ovf0 flag is 1, clear it to 0. because the tp0ovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tp0ccr1 register. read the tp0ovf1 flag. if the tp0ovf1 flag is 1, clear it to 0 (the tp0ovf0 flag is cleared in <4>, and the tp0ovf1 flag remains 1). because the tp0ovf1 flag is 1, the puls e width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 256 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tp0ce bit inttp0ov signal tp0ovf bit tp0ovf0 flag note tip00 pin input tp0ccr0 register tp0ovf1 flag note tip01 pin input tp0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tp0ovf0 and tp0ovf1 flags are set on the internal ram by software. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tp0ccr0 register. read the overflow flag. if the overflow flag is 1, set only the tp0ovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tp0ccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tp0ovf1 flag. if the tp0ovf1 flag is 1, clear it to 0. because the tp0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 257 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0ov signal tp0ovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tp0ccra register (setting of t he default value of the tip0a pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tp0ccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 258 example when capture trigger interval is long ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0ov signal tp0ovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tp0ccra register (setting of t he default value of the tip0a pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tp0ccra register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h). chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 259 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tp0ovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tp0opt0 regist er. to accurately detect an overflow, read the tp0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tp0ovf bit) overflow flag (tp0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 260 7.5.7 pulse width measurement mode (tp0md2 to tp0md0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter p starts counting when the tp0ctl0.tp0ce bit is set to 1. each time the valid edge input to the tip0a pi n has been detected, the count va lue of the 16-bit counter is stored in the tp0ccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readin g the tp0ccra register after a capture interrupt request signal (inttp0cca) occurs. select either the tip00 or tip01 pin as the capture trigger input pin. specify ?no edge detected? by using the tp0ioc1 register for the unused pins. when an external clock is used as the count clock, measur e the pulse width of the tip01 pin because the external clock is fixed to the tip00 pin. at this time, clear the tp0ioc1.tp0is1 and tp0ioc1.tp0is0 bits to 00 (capture trigger input (tip00 pin): no edge detected). figure 7-34. configuration in pulse width measurement mode tp0ccr0 register (capture) tp0ce bit tp0ccr1 register (capture) edge detector count clock selection edge detector edge detector tip00 pin (external event count input/capture trigger input) tip01 pin (capture trigger input) internal count clock clear inttp0ov signal inttp0cc0 signal inttp0cc1 signal 16-bit counter digital noise eliminator digital noise eliminator remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 261 figure 7-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0cca signal inttp0ov signal tp0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark a = 0, 1 when the tp0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tip0a pin is later detected, the count value of the 16-bit counter is stored in the tp0ccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttp0cca) is generated. the pulse width is calculated as follows. first pulse width = (d 0 + 1) count clock cycle second and subsequent pulse width = (d n ? d n ? 1 ) count clock cycle if the valid edge is not input to the tip0a pin even wh en the 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttp0ov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tp0opt0.t p0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. first pulse width = (d 0 + 10001h) count clock cycle second and subsequent pulse width = (10000h + d n ? d n ? 1 ) count clock cycle remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 262 figure 7-36. register setting in pu lse width measurement mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note setting is invalid when the tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 110 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tp0cks0 to tp0cks2 bits 1: count external event count input signal (c) tmp0 i/o control register 1 (tp0ioc1) 0 0 0 0 0/1 tp0ioc1 select valid edge of tip00 pin input select valid edge of tip01 pin input 0/1 0/1 0/1 tp0is2 tp0is1 tp0is0 tp0is3 (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 263 figure 7-36. register setting in pu lse width measurement mode (2/2) (e) tmp0 option register 0 (tp0opt0) 00000 tp0opt0 overflow flag 0 0 0/1 tp0ccs0 tp0ovf tp0ccs1 (f) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (g) tmp0 capture/compare regist ers 0 and 1 (tp0ccr0 and tp0ccr1) these registers store the count valu e of the 16-bit counter when the valid edge input to the tip0a pin is detected. remarks 1. tmp0 i/o control register 0 (tp0ioc0) is not used in the pulse wid th measurement mode. 2. a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 264 (1) operation flow in pul se width measurement mode figure 7-37. software processing flow in pulse width measurement mode <1> <2> set tp0ctl0 register (tp0ce bit = 1) tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits), tp0ctl1 register, tp0ioc1 register, tp0ioc2 register, tp0opt0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal d 0 0000h 0000h d 1 d 2 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 265 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tp0ovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tp0opt0 regist er. to accurately detect an overflow, read the tp0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tp0ovf bit) overflow flag (tp0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 266 7.5.8 timer output operations the following table shows the operations and out put levels of the top00 and top01 pins. table 7-4. timer output control in each mode operation mode top01 pin top00 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? table 7-5. truth table of top00 and top01 pins under control of timer output control bits tp0ioc0.tp0ola bit tp0ioc0.tp0oea bit tp0ctl0.tp0ce bit level of top0a pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark a = 0, 1 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 267 7.6 eliminating noise on captur e trigger input pin (tip0a) the tip0a pin has a digital noise eliminator. however, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is used as an external event count input pin or external trigger input pin. digital noise can be eliminated by specifying the alter nate function of the tip0a pi n using the pmc3, pfc3, and pfce3 registers. the number of times of sampling can be selected from three or two by using the panfc.panfsts bit. the sampling clock can be selected from f xx , f xx /2, f xx /4, f xx /16, f xx /32, or f xx /64, by using the panfc.panfc2 to panfc.panfc0 bits. (1) tip0a noise elimination control register (panfc) this register is used to select the sampling clock and t he number of times of sampling for eliminating digital noise. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 panfc (a = 0, 1) panfsts 0 0 0 panfc2 panfc1 panfc0 number of times of sampling = 3 number of times of sampling = 2 panfsts 0 1 setting of number of times of sampling for eliminating digital noise after reset: 00h r/w address: p0nfc fffffb00h, p1nfc fffffb04h f xx f xx /2 f xx /4 f xx /16 f xx /32 f xx /64 panfc2 0 0 0 0 1 1 panfc1 0 0 1 1 0 0 panfc0 0 1 0 1 0 1 sampling clock selection setting prohibited other than above cautions 1. enable starting the 16-bit counter of tmp0 (tp0ctl.tp0ce bit = 1) after the lapse of the sampling clock period number of times of sampling. 2. be sure to clear bits 7, 5 to 3 to 0. chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 268 chapter 7 16-bit timer/event counter p (tmp) preliminary user?s manual u16895ej1v0ud 269 7.7 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh, not 0000h, may be captured in the tp0ccrn register if the capture trigger is input immediately after the tp0ce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tp0ce bit tp0ccr0 register ffffh 0001h 0000h tip00 pin input capture trigger input 16-bit counter sampling clock capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tp0ce bit tp0ccr0 register tip00 pin input capture trigger input 16-bit counter sampling clock capture trigger input preliminary user?s manual u16895ej1v0ud 270 chapter 8 16-bit timer/event counter 0 in the v850es/kf1+, two channels of 16-bi t timer/event counter 0 are provided. 8.1 functions 16-bit timer/event counter 0n has the following functions (n = 0, 1). (1) interval timer generates an interrupt at predetermined time intervals. (2) ppg output can output a rectangular wave with any frequency and any output pulse width. (3) pulse width measurement can measure the pulse width of a signal input from an external source. (4) external event counters can measure the number of pulses of a signal input from an external source. (5) square-wave output can output a square wave of any frequency. (6) one-shot pulse output can output a one-shot pulse with any output pulse width. 8.2 configuration 16-bit timer/event counter 0n consis ts of the following hardware. table 8-1. configuration of 16- bit timer/event counter 0n item configuration timer/counters 16-bi t timer counter 0n 1 (tm0n) registers 16-bit timer captur e/compare register: 16 bits 2 (cr0n0, cr0n1) timer inputs 2 (ti0n0, ti0n1 pins) timer outputs 1 (to0n pin), output controller control registers note 16-bit timer mode control register n (tmc0n) capture/compare control register n (crc0n) 16-bit timer output control register n (toc0n) prescaler mode register 0n (prm0n) selector operation control register 1 (selcnt1) note to use the ti0n0, ti0n1, and to0n pin functions, refer to table 4-14 settings when port pins are used for alternate functions . remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 271 the block diagram is shown below. figure 8-1. block diagram of 16- bit timer/event counter 0n inttm0n0 to0n inttm0n1 tl0n1 f xx /4 tl0n0 2 crc0n2 crc0n2 crc0n1 crc0n0 tmc0n3 tmc0n2 tmc0n1 ovf0n ospt0n ospe0n toc0n4 lvs0n lvr0n toc0n1 toe0n match clear noise eliminator noise eliminator 16-bit timer capture/compare register 0n0 (cr0n0) 16-bit timer capture/compare register 0n1 (cr0n1) 16-bit timer counter 0n (tm0n) match internal bus count clock note capture/compare control register 0n (crc0n) output controller selector timer output control register 0n (toc0n) noise eliminator 16-bit timer mode control register 0n (tmc0n) selector selector internal bus selector prescaler mode register 0n (prm0n) selector operation control register 1 (selcnt1) prm0n1 isel1n prm0n0 note set with the prm0n regi ster and selcnt1 register. remarks 1. n = 0, 1 2. f xx : main clock frequency chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 272 (1) 16-bit timer counter 0n (tm0n) the tm0n register is a 16-bit read-onl y register that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. tm0n (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r address: tm00 fffff600h, tm01 fffff610h 14 0 13 11 9 7 5 3 15 1 the count value is reset to 0000h in the following cases. <1> reset <2> if the tmc0n.tmc0n3 and tmc0n.tmc0n2 bits are cleared (0). <3> if the valid edge of the ti0n0 pin is input in the mode in which clear & start occurs when inputting the valid edge of the ti0n0 pin <4> if the tm0n register and the cr0n0 register match eac h other in the mode in which clear & start occurs on a match between the tm0n register and the cr0n0 register <5> if the toc0n.ospt0n bit is set (1) or if the valid edge of the ti0n0 pin is input in the one-shot pulse output mode remark n = 0, 1 (2) 16-bit timer capture/comp are register 0n0 (cr0n0) the cr0n0 register is a 16-bit register that combines capture register and compare register functions. the crc0n.crc0n0 bit is used to set whether to use the cr0n0 register as a ca pture register or as a compare register. the cr0n0 register can be read or written in 16-bit units. after reset, this register is cleared to 0000h. cr0n0 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: cr000 fffff602h, cr010 fffff612h 14 0 13 11 9 7 5 3 15 1 (a) when using the cr0n0 register as a compare register the value set to the cr0n0 register and the count value set to the tm0n register are always compared and when these values match, an interrupt request si gnal (inttm0n0) is generated. the values are retained until rewritten. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 273 (b) when using the cr0n0 regist er as a capture register the tm0n register count value is captured to the cr0n0 register by inputting a capture trigger. the valid edge of the ti0n0 pin or ti0n1 pin can be selected as the captur e trigger. the valid edge of the ti0n0 pin is set with the prm0n.esn 01 and prm0n.esn00 bits. the va lid edge of the ti0n1 pin is set with the prm0n.esn11 and prm0n.esn10 bits. table 8-2 shows the settings when the valid edge of the ti0n0 pin is specified as the capture trigger, and table 8-3 shows the settings when the valid edge of the ti0n1 pin is specified as the capture trigger. table 8-2. capture trigger of cr0n0 register and valid edge of ti0n0 pin capture trigger of cr0n0 valid edge of ti0n0 pin esn01 esn00 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 remarks 1. n = 0, 1 2. setting the esn01 and esn00 bits to 10 is prohibited. table 8-3. capture trigger of cr0n0 register and valid edge of ti0n1 pin capture trigger of cr0n0 valid edge of ti0n1 pin esn11 esn10 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. n = 0, 1 2. setting the esn11 and esn10 bits to 10 is prohibited. cautions 1. set a value other than 0000h to the cr0n0 register in the mode in which clear & start occurs upon a match of the values of th e tm0n register and cr0n0 register. however, if 0000h is set to th e cr0n0 register in the fr ee-running timer mode or the ti0n0 pin valid edge clear & start mode, an interrupt request signal (inttm0n0) is generated when the value cha nges from 0000h to 0001h afte r an overflow (ffffh). 2. when the p33 and p35 pins are used as the valid edges of ti000 and ti010, and the timer output function is used, set the p34 and p32 pins as the timer output pins (to00, to01). 3. if, when the cr0n0 register is used as a capture register, the re gister read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. the cr0n0 register cannot be rewr itten during timer count operation. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 274 (3) 16-bit timer capture/comp are register 0n1 (cr0n1) the cr0n1 register is a 16-bit register that combines capture register and compare register functions. the crc0n.crc0n2 bit is used to set whether to use the cr0n1 register as a capture re gister or as a compare register. the cr0n1 register can be read or written in 16-bit units. after reset, this register is cleared to 0000h. cr0n1 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: cr001 fffff604h, cr011 fffff614h 14 0 13 11 9 7 5 3 15 1 (a) when using the cr0n1 register as a compare register the value set to the cr0n1 regist er and the count value of the tm 0n register are always compared and when these values match, an interrupt re quest signal (inttm0n1) is generated. (b) when using the cr0n1 regist er as a capture register the tm0n register count value is captured to the cr0n1 register by inputting a capture trigger. the valid edge of the ti0n0 pin can be selected as the capture trigger. the valid edge of the ti0n0 pin is set with the prm0n.esn01 and prm0n.esn00 bits. table 8-4 shows the settings when the valid edge of t he ti0n0 pin is specified as the capture trigger. table 8-4. capture trigger of cr0n1 register and valid edge of ti0n0 pin capture trigger of cr0n1 valid edge of ti0n0 pin esn01 esn00 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. n = 0, 1 2. setting the esn01 and esn00 bits to 10 is prohibited. cautions 1. if 0000h is set to the cr0n1 regist er, an interrupt request signal (inttm0n1) is generated after overflow of the tm0n regi ster, after clear & start on a match between the tm0n register and cr0n0 register, after clear by the valid edge of the ti0n0 pin, or after clear by a one-shot pulse output trigger. 2. when the p33 and p35 pins are used as the valid edges of ti000 and ti010, and the timer output function is used, set the p34 and p32 pins as the timer output pins (to00, to01). 3. if, when the cr0n1 register is used as a capture register, the re gister read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. the cr0n1 register can be rewritten dur ing tm0n register operation only in the ppg output mode. refer to 8.4.2 ppg output operation. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 275 8.3 registers the registers that control 16-bit time r/event counter 0n are as follows. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare contro l register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) ? selector operation control register 1 (selcnt1) remark to use the ti0n0, ti0n1, and to0n pin functions, refer to table 4-14 settings when port pins are used for alternate functions . (1) 16-bit timer mode contro l register 0n (tmc0n) the tmc0n register is used to set the operation mode of 16-bit timer/event counter 0n, the clear mode of the tm0n register, the output timing, and to detect overflow. the tmc0n register can be read or written in 8-bit or 1-bit units. after reset, this register is cleared to 00h. cautions 1. 16-bit timer/event counter 0n starts ope rating when a value other than 00 (operation stop mode) is set to the tmc0n.tmc0n3 and tmc0 n.tmc0n2 bits. to stop the operation, set 00 to the tmc0n3 and tmc0n2 bits. 2. when the main clock is stopped and the cpu operates on the subclock, do not access the tmc0n register using an access method that causes a wait. for details, refer to 3.4.8 (2). remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 276 7 0 operation stop (tm0n cleared to 0) free-running timer mode clear & start with valid edge of ti0n0 clear & start upon match of tm0n and cr0n0 unchanged match of tm0n and cr0n0 or match of tm0n and cr0n1 match of tm0n and cr0n0, match of tm0n and cr0n1, or valid edge of ti0n0 match of tm0n and cr0n0 or match of tm0n and cr0n1 match of tm0n and cr0n0, match of tm0n and cr0n1, or valid edge of ti0n0 match of tm0n and cr0n0 or match of tm0n and cr0n1 match of tm0n and cr0n0, match of tm0n and cr0n1, or valid edge of ti0n0 not generated generated upon match of tm0n and cr0n0 and match of tm0n and cr0n1 tmc0n3 0 0 0 0 1 1 1 1 selection of operation mode and clear mode selection of to0n output inverse timing (n = 0, 1) 6 0 5 0 4 0 3 tmc0n3 2 tmc0n2 1 tmc0n1 note <0> ovf0n tmc0n2 0 0 1 1 0 0 1 1 tmc0n1 note 0 1 0 1 0 1 0 1 after reset: 00h r/w address: tmc00 fffff606h, tmc01 fffff616h no overflow overflow ovf0n 0 1 detection of overflow of 16-bit timer register 0n tmc0n generation of interrupt note be sure to clear the tmc0n1 bit to 0 when the to0n pin and ti0n0 pin are used alternately. cautions 1. write to bits other than the ov f0n flag after stopping the timer operation. 2. the valid edge of the ti0n0 pi n is set by the prm0n register. 3. when the mode in whic h the timer is cleared and st arted upon match of tm0n and cr0n0 is selected, the setting value of cr0n0 is ffffh, and when the value of tm0n changes from ffffh to 0000h, the ovf0n flag is set to 1. remark to0n: output pin of 16-b it timer/event counter 0n ti0n0: input pin of 16-bit timer/event counter 0n tm0n: 16-bit timer counter 0n cr0n0: 16-bit timer capture/compare register 0n0 cr0n1: 16-bit timer capture/compare register 0n1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 277 (2) capture/compare control register 0n (crc0n) the crc0n register controls the operation of the cr0n0 and cr0n1 registers. the crc0n register can be read or written in 8-bit or 1-bit units. after reset, crc0n is cleared to 00h. 7 0 operation as compare register operation as capture register crc0n2 0 1 selection of operation mode of cr0n1 register crc0n 6 0 5 0 4 0 3 0 2 crc0n2 1 crc0n1 0 crc0n0 after reset: 00h r/w address: crc00 fffff608h, crc01 fffff618h capture at valid edge of ti0n1 pin capture at inverse phase of valid edge of ti0n0 pin crc0n1 0 1 selection of capture trigger of cr0n0 register operation as compare register operation as capture register crc0n0 0 1 selection of operation mode of cr0n0 register (n = 0, 1) cautions 1. before setting the crc0n regist er, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started upon match of the tm0n register and cr0n0 register is selected by the tmc0n register, do not specify the cr0n0 register as the capture register. 3. when both the rising and falling edges ar e specified for the ti 0n0 pin valid edge, capture operation is not performed. 4. to ensure reliable capture operation, a pulse longer than tw o cycles of the count clock selected by the prm0n and sel cnt1 registers is required. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 278 (3) 16-bit timer output control register 0n (toc0n) the toc0n register controls the operation of the 16-bit timer/event counter 0n output controller by setting or resetting the timer output f/f, enabling or disabling inve rse output, enabling or disabling the timer of 16-bit timer/event counter 0n, enabling or disabling the one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software. the toc0n register can be read or written in 8-bit or 1-bit units. after reset, toc0n is cleared to 00h. (1/2) 0 ? one-shot pulse output ospt0n 0 1 output trigger for one-shot pulse by software toc0n ospt0n ospe0n toc0n4 lvs0n lvr0n toc0n1 toe0n successive pulse output one-shot pulse output note ospe0n 0 1 control of one-shot pulse output operation inversion operation disabled inversion operation enabled toc0n4 0 1 control of timer output f/f upon match of cr0n1 register and tm0n register after reset: 00h r/w address: toc00 fffff609h, toc01 fffff619h (n = 0, 1) 7 <6> <5> 4 <3> <2> 1 <0> inversion operation disabled inversion operation enabled toc0n1 0 1 control of timer output f/f upon match of cr0n0 register and tm0n register output disabled (output is fixed to low level) output enabled toe0n 0 1 control of timer output unchanged reset timer output f/f (0) set timer output f/f (1) setting prohibited lvs0n 0 0 1 1 setting of status of timer output f/f lvr0n 0 1 0 1 note the one-shot pulse output operates normally in the free-running timer mode and the mode in which clear & start occurs on the valid edge of the ti0n0 pin. in the mode in which clear & start occurs on match between the tm0n register and the cr0n0 register, one-shot pulse output is not performed because no overflow occurs. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 279 (2/2) cautions 1. be sure to stop the timer operat ion before setting other than the toc0n4 bit. 2. the lvs0n and lvr0n bits are 0 when read. 3. the ospt0n bit is 0 when read because it is automatically cleared after data has been set. 4. do not set the ospt0n bit (1) other than for one-shot pulse output. 5. when performing successive writes to the ospt0n bit, place an interval between writes of two or more cycles of the coun t clock selected by the prm0n register. 6. do not set the lvs0n bit (1) before setting the toe0n bit. do not set the lvs0n bit and toe0n bit (1) at the same time. 7. do not set <1> and <2> below at the same time. set as follows. <1> set the toc0n1, to c0n4, toe0n, and ospe0n bi ts: setting of timer output operation <2> set the lvs0n and lvr0n bits: setting of timer output f/f chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 280 (4) prescaler mode register 0n (prm0n) the prm0n register sets the count clock of the tm0n register and the valid edge of the ti0n0 and ti0n1 pin inputs. the prmn01 and prmn00 bits are set in combination with the selcnt1.isel1n bit. refer to 8.3 (6) count clock setting for 16-bit timer/event counter 0n for details. the prm0n register can be read or written in 8-bit or 1-bit units. after reset, prm0n is cleared to 00h. cautions 1. when setting the count clock to the ti 0n0 pin valid edge, do not set the mode in which clear & start occurs on ti0n0 pin valid edge and do not set the ti0n0 pin as a capture trigger. 2. before setting the pr m0n register, be sure to stop the timer operation. 3. if 16-bit timer/event counter 0n operation is enabled by specifying the rising edge or both edges for the valid edge of the ti0n0 pin or ti0n1 pin while the ti0n0 pin or ti0n1 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. be careful when pulling up the ti0n0 pin or ti0n1 pin. however, the rising edge is not detected when operation is enabled after it has been stopped. 4. when the p33 and p35 pins are used as the valid edges of ti000 and ti010, and the timer output function is used, set the p34 and p32 pins as the timer output pins (to00, to01). esn11 falling edge rising edge setting prohibited both rising and falling edges esn11 0 0 1 1 selection of valid edge of ti0n1 prm0n (n = 0, 1) esn10 esn01 esn00 0 0 prmn01 prmn00 esn10 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges esn01 0 0 1 1 selection of valid edge of ti0n0 esn00 0 1 0 1 76 54 32 1 0 after reset: 00h r/w address: prm00 fffff607h, prm01 fffff617h chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 281 (5) selector operation control register 1 (selcnt1) the selcnt1 register sets the count cl ock of 16-bit timer/event counter 0n. the selcnt1 register can be read or written in 8-bit or 1-bit units. after reset, selcnt1 is cleared to 00h. the selcnt1 register is set in combination with t he prm0n.prmn01 and prm0n.prmn00 bits. refer to 8.3 (6) count clock setting for 16-bit timer/event counter 0n for details. 0 selcnt1 0 0 0 0 0 isel11 isel10 after reset: 00h r/w address: fffff30ah 76 54 32 1 0 (6) count clock setting for 16- bit timer/event counter 0n the count clock for 16-bit timer/event counter 0n is set by using the prm0n.prmn01, prm0n.prmn00, and selcnt1.isel1n bits in combination. (a) count clock for 16-bit timer/event counter 00 selcnt1 register prm00 register selection of count clock note 1 isel10 bit prm001 bit prm000 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 f xx /2 100 ns 125 ns 200 ns 0 0 1 f xx /4 200 ns 250 ns 400 ns 0 1 0 f xx /8 400 ns 500 ns 800 ns 0 1 1 valid edge of ti000 note 2 ? ? ? 1 0 0 f xx /32 1.6 s 2.0 s 3.2 s 1 0 1 f xx /64 3.2 s 4.0 s 6.4 s 1 1 0 f xx /128 6.4 s 8.0 s 12.8 s 1 1 1 setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions: v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = capacity: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse lon ger than two cycles of the internal clock (f xx /4). chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 282 (b) count clock for 16-bit timer/event counter 01 selcnt1 register prm01 register selection of count clock note 1 isel11 bit prm011 bit prm010 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 f xx setting prohibited setting prohibited 100 ns 0 0 1 f xx /4 200 ns 250 ns 400 ns 0 1 0 intwt ? ? ? 0 1 1 valid edge of ti010 note 2 ? ? ? 1 0 0 f xx /2 100 ns 125 ns 200 ns 1 0 1 f xx /8 400 ns 500 ns 800 ns 1 1 0 f xx /16 800 ns 1.0 s 1.6 s 1 1 1 setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions: v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = capacity: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse lon ger than two cycles of the internal clock (f xx /4). chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 283 8.4 operation 8.4.1 operation as interval timer 16-bit timer/event counter 0n can be m ade to operate as an interval timer by setting the tmc0n register and the crc0n register as shown in figure 8-2. setting procedure the basic operation setting procedure is as follows. <1> set the count clock using the pr m0n register and the selcnt1 register. <2> set the crc0n register (refer to figure 8-2 for the setting value). <3> set any value to the cr0n0 register. <4> set the tmc0n register: start operation (refer to figure 8-2 for the setting value). caution the cr0n0 register cannot be rewritten during 16-bit time r/event counter 0n operation. remarks 1. for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions . 2. for inttm0n0 interrupt enable, refer to chapter 19 interrupt/exception processing function . the interval timer repeatedly generates in terrupts at the interval of the preset count value in the cr0n0 register. if the count value in the tm0n register matches the value set in the cr0n0 register, an interrupt request signal (inttm0n0) is generated at the same time that the value of the tm 0n register is cleared to 0000h and counting is continued. the count clock of 16-bit timer/event counter 0n can be selected with the prm 0n.prm0n0, prm0n.prm0n1, and selcnt1.isel1n bits. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 284 figure 8-2. control register settings in interval timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 0 tmc0n 000110/1 note 0 tmc0n3 tmc0n2 tmc0n1 ovf0n clears & starts upon match between tm0n and cr0n0 (b) capture/compare cont rol register 0n (crc0n) 0 crc0n 00000/10/10 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register note be sure to clear the tmc0n1 bit to 0 when the to0n pin and ti0n0 pin are used alternately. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the interval timer function. for details, refer to 8.3 (1) 16-bit timer mode control register 0n (tmc0n) and 8.3 (2) capture/compare control register 0n (crc0n) . 2. n = 0, 1 figure 8-3. configuration of interval timer 16-bit timer capture/compare register 0n0 (cr0n0) 16-bit timer counter 0n (tm0n) selector ovf0n inttm0n0 count clock note ti0n0 clear circuit noise eliminator f xx /4 note set with the prm0n regist er and selcnt1 register. remarks 1. f xx : main clock frequency 2. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 285 figure 8-4. timing of interval timer operation t interval time interval time 0000h n 0001h 0001h 0000h nn n n n n 0001h 0000h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm0n count value cr0n0 inttm0n0 timer operation enable remarks 1. interval time = (n + 1) t: n = 0001h to ffffh 2. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 286 8.4.2 ppg output operation 16-bit timer/event counter 0n can be used for ppg (progr ammable pulse generator) ou tput by setting the tmc0n register and the crc0n register as shown in figure 8-5. setting procedure the basic operation setting procedure is as follows. <1> set the crc0n register (refer to figure 8-5 for the setting value). <2> set any value as a cycle to the cr0n0 register. <3> set any value as a duty to the cr0n1 register. <4> set the toc0n register (refer to figure 8-5 for the setting value). <5> set the count clock using the prm0n register and selcnt1 register. <6> set the tmc0n register: start operation (refer to figure 8-5 for the setting value). caution to change the duty value (cr0 n1 register) during operation, refe r to remark 2 in figure 8-7 ppg output operation timing. remarks 1. for the alternate-function pin (to0n) settings, refer to table 4-14 settings when port pins are used for alternate functions . 2. for inttm0n0 interrupt enable, refer to chapter 19 interrupt/exception processing function . the ppg output function outputs a rectangular wave from the to0n pin with the cycle s pecified by the count value set in advance to the cr0n0 register and the pulse width s pecified by the count value set in advance to the cr0n1 register. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 287 figure 8-5. control register settings in ppg output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts upon match between tm0n and cr0n0 100 (b) capture/compare cont rol register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as compare register 0 : don't care 0 (c) 16-bit timer output control register 0n (toc0n) 0 0 0 1 0/1 toc0n enables to0n output inverts output upon match between tm0n and cr0n0 specifies initial value of to0n output f/f inverts output upon match between tm0n and cr0n1 disables one-shot pulse output 0/1 1 1 lvr0n toc0n1 toe0n ospe0n ospt0n toc0n4 lvs0n (d) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 0/1 0/1 0/1 0/1 0 3 prm0n 2 prm0n1 prm0n0 esn11 esn10 esn01 esn00 selects count clock setting invalid (setting to 10 is prohibited.) setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 isel1n 0/1 selcnt1 cautions 1. make sure that 0000h cr0n1 < cr0n0 ffffh is set to the cr0n0 register and cr0n1 register. 2. the cycle of the pulse generated by ppg output is (cr0n0 setting value + 1). the duty factor is (cr0n1 setting val ue + 1) / (cr0n0 setting value + 1). remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 288 figure 8-6. configuration of ppg output f xx /4 ti0n0 to0n 16-bit capture/compare register 0n1 (cr0n1) 16-bit capture/compare register 0n0 (cr0n0) count clock note selector noise eliminator 16-bit timer counter 0n (tm0n) clear circuit output controller note the count clock is set with the prm0n register and selcnt1 register. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 289 figure 8-7. ppg output operation timing t 0000h 0000h 0001h 0001h m ? 1 to0n n m m n ? 1 n count clock tm0n count value value loaded to cr0n0 value loaded to cr0n1 clear clear pulse width: (m + 1) t 1 cycle: (n + 1) t n caution the cr0n0 register cannot be rewritten during 16-bit time r/event counter 0n operation. remarks 1. 0000h m < n ffffh 2. change the pulse width during 16-bit timer/event counter 0n operation (rewrite cr0n1 register) as follows in a ppg output operation. <1> disable the timer output inversion operation based on a match of the tm0n and cr0n1 registers (toc0n4 bit = 0). <2> disable the inttm0n1 interrupt (tm0mkn1 bit =1). <3> rewrite the cr0n1 register. <4> wait for a cycle of the tm0n register count clock. <5> enable the timer output inversion o peration based on a match of the tm0n and cr0n1 registers (toc0n4 bit = 1). <6> clear the interrupt request flag of inttm0n1 (tm0ifn1 bit = 0). <7> enable the inttm0n1 interrupt (tm0mkn1 bit = 0). 3. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 290 8.4.3 pulse width measurement the tm0n register can be used to meas ure the pulse widths of the signals input to the ti0n0 and ti0n1 pins. measurement can be carried out with 16-b it timer/event counter 0n used in the free-running timer mode or by restarting the timer in synchronization with the edge of the signal input to the ti0n0 pin. when an interrupt is generated, read the valid capture re gister value. after confi rming the tmc0n.ovf0n flag, clear it (0) by software and measure the pulse width. setting procedure the basic operation setting procedure is as follows. <1> set the crc0n register (refer to figures 8-9 , 8-12 , 8-14 , and 8-16 for the setting value). <2> set the count clock using the prm0n register and selcnt1 register. <3> set the tmc0n register: start operation (refer to figures 8-9 , 8-12 , 8-14 , and 8-16 for the setting value). caution when using two capture regist ers, set the ti0n0 and ti0n1 pins. remarks 1. for the alternate-function pin (ti0n0, ti0n1) settings, refer to table 4-14 settings when port pins are used for alternate functions . 2. for inttm0n0 and inttm0n1 interrupt enable, refer to chapter 19 interrupt/exception processing function . figure 8-8. cr0n1 capture operati on with rising edge specified n ? 3n ? 2n ? 1 n n + 1 n count clock tm0n cr0n1 inttm0n1 ti0n0 rising edge detection remarks 1. n = 0, 1 2. the valid edge is detected through sampling at a count clock cycle selected with the prm0n register and selcnt1 register, and the capture operation is not performed until the valid edge is detected twice. as a result, noise wit h a short pulse width can be eliminated. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 291 (1) pulse width measurement with free-running timer operation and one capture register if the edge specified by the prm0n regi ster is input to the ti0n0 pin when 16-bit timer/event counter 0n is operated in the free-running timer mode (refer to figure 8-9 ), the value of the tm0n register is loaded to the cr0n1 register and an external interrupt request signal (inttm0n1) is generated. the valid edge is specified by t he prm0n.esn00 and prm0n.esn01 bits. the rising edge, falling edge, or both the rising and falling edges can be selected. the valid edge is detected throu gh sampling at a count clock cycle se lected with the prm0n register and selcnt1 register, and the capture oper ation is not performed until the valid edge is detected twice. as a result, noise with a short pulse width can be eliminated. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 292 figure 8-9. control register setti ngs for pulse width measurement with free-running timer operati on and one capture register (when ti0n0 pin and cr0n1 register are used) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n free-running timer mode 1 0/1 note 0 (b) capture/compare cont rol register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as capture register 1 0/1 0 (c) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 0/1 0/1 1 1 0 prm0n selects count clock (setting to 111 is prohibited.) specifies both edges for pulse width detection setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 0/1 2 prm0n1 prm0n0 esn01 esn10 esn11 esn00 3 isel1n selcnt1 note be sure to clear the tmc0n1 bit to 0 when the to0n pin and ti0n0 pin are used alternately. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. for details, refer to 8.3 (1) 16-bit timer mode control register 0n (tmc0n) and 8.3 (2) capture/compare control register 0n (crc0n) . 2. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 293 figure 8-10. configuration fo r pulse width measurement with free-running timer operation 16-bit timer counter 0n (tm0n) 16-bit timer capture/compare register 0n1 (cr0n1) selector ovf0n inttm0n1 internal bus ti0n0 count clock note note the count clock is set with the pr m0n register and selcnt1 register. remark n = 0, 1 figure 8-11. timing of pulse width measu rement with free-running timer operation and one capture register ( with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 + 1 d1 d0 d1 d2 d3 d2 d3 d1 + 1 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t count clock tm0n count value ti0n0 pin input value loaded to cr0n1 inttm0n1 ovf0n cleared by instruction remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 294 (2) measurement of two pulse width s with free-running timer operation the pulse widths of two signals respectively input to the ti0n0 pin and the ti0n1 pi n can be simultaneously measured when 16-bit timer/event counter 0n is used in the free-running timer mode (refer to figure 8-12 ). when the edge specified by the prm 0n.esn00 and prm0n.esn01 bits is input to the ti0n0 pin, the value of the tm0n register is loaded to the cr0n1 register and an external inte rrupt request signal (inttm0n1) is generated. when the edge specified by the prm 0n.esn10 and prm0n.esn11 bits is input to the ti0n1 pin, the value of the tm0n register is loaded to the cr0n0 register and an external inte rrupt request signal (inttm0n0) is generated. the edges of the ti0n0 and ti0n1 pi ns are specified by the prm0n. esn00 and prm0n.esn01 bits and the prm0n.esn10 and prm0n.esn11 bits, respectively. specify both rising and falling edges. the valid edge of the ti0n0 pin is det ected through sampling at the count clock cycle selected with the prm0n register and selcnt1 register, and t he capture operation is not performed until the valid level is detected twice. as a result, noise with a short pulse width can be eliminated. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 295 figure 8-12. control register settings for measurement of two pulse widths with free-running timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 0 tmc0n 000010/1 note 0 tmc0n3 tmc0n2 tmc0n1 ovf0n free-running timer mode (b) capture/compare cont rol register 0n (crc0n) 0 crc0n 0000101 crc0n2 crc0n1 crc0n0 cr0n0 used as capture register captures to cr0n0 at valid edge of ti0n1 pin cr0n1 used as capture register (c) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 11110 prm0n selects count clock (setting to 111 is prohibited.) specifies both edges for pulse width detection. specifies both edges for pulse width detection. 0 0/1 0/1 2 prm0n1 prm0n0 esn01 esn10 esn11 esn00 3 0/1 isel1n selcnt1 note be sure to clear the tmc0n1 bit to 0 when the to0n pin and ti0n0 pin are used alternately. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. for details, refer to 8.3 (1) 16-bit timer mode control register 0n (tmc0n) . 2. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 296 ? capture operation (free-running timer mode) the following figure illustrates the operation of the c apture register when the capture trigger is input. figure 8-13. timing of pulse width measu rement with free-running timer operation (with both edges specified) t 0000h 0001h ffffh 0000h d0 d0 + 1 d1 d0 d1 d1 d2 + 1 d2 d1 + 1 d2 d3 d2 + 1 d2 + 2 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t count clock tm0n count value ti0n0 pin input ti0n1 pin input value loaded to cr0n1 value loaded to cr0n0 inttm0n1 inttm0n0 ovf0n cleared by instruction remark n = 0, 1 (3) pulse width measurement with free-running timer operation and two capture registers when 16-bit timer/event counter 0n is used in the free-running timer mode (refer to figure 8-14 ), the pulse width of the signal input to the ti0n0 pin can be measured. when the edge specified by the prm 0n.esn00 and prm0n.esn01 bits is input to the ti0n0 pin, the value of the tm0n register is loaded to the cr0n1 register and an external inte rrupt request signal (inttm0n1) is generated. the value of the tm0n register is al so loaded to the cr0n0 register wh en an edge inverse to the one that triggers capturing to the cr0n1 register is input. the valid edge of the ti0n0 pin is detected through sampling at a count clock cycle selected with the prm0n register and selcnt1 register, and t he capture operation is not performed until the valid edge is detected twice. as a result, noise with a short pulse width can be eliminated. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 297 figure 8-14. control register setti ngs for pulse width measurement with free-running timer operati on and two capture registers (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0 tmc0n 000010/1 note 0 tmc0n3 tmc0n2 tmc0n1 ovf0n free-running timer mode (b) capture/compare cont rol register 0n (crc0n) 0 crc0n 0000111 crc0n2 crc0n1 crc0n0 cr0n0 used as capture register captures to cr0n0 at edge inverse to valid edge of ti0n0 pin cr0n1 used as capture register (c) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 0/1 0/1 0 1 0 3 prm0n 2 prm0n1 prm0n0 esn11 esn10 esn01 esn00 selects count clock (setting to 111 is prohibited.) specifies rising edge for pulse width detection setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 0/1 isel1n selcnt1 note be sure to clear the tmc0n1 bit to 0 when the to0n pin and ti0n0 pin are used alternately. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. for details, refer to 8.3 (1) 16-bit timer mode control register 0n (tmc0n) . 2. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 298 figure 8-15. timing of pulse width measu rement with free-running timer operation and two capture registers (with rising edge specified) t 0000h 0001h ffffh 0000h d0 d0 d1 d3 d2 d0 + 1 d1 d1 + 1 d2 d3 d2 + 1 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t count clock tm0n count value ti0n0 pin input value loaded to cr0n1 value loaded to cr0n0 inttm0n1 ovf0n cleared by instruction remark n = 0, 1 (4) pulse width measurement by restarting when the valid edge of the ti0n0 pin is detected, the pulse width of the signal input to the ti0n0 pin can be measured by clearing the tm0n regist er and then resuming counting after l oading the count value of the tm0n register to the cr0n1 register (refer to figure 8-17 ). the edge is specified by the prm0n.esn00 and pr m0n.esn01 bits. the rising or falling edge can be specified. the valid edge is detected throu gh sampling at a count clock cycle se lected with the prm0n register and selcnt1 register, and the capture operat ion is not performed until the valid level is detected twice. as a result, noise with a short pulse width can be eliminated. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 299 figure 8-16. control register settings fo r pulse width measurement by restarting (a) 16-bit timer mode cont rol register 0n (tmc0n) 0 tmc0n 000100/1 note 0 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts at valid edge of ti0n0 pin (b) capture/compare cont rol register 0n (crc0n) 0 crc0n 0000111 crc0n2 crc0n1 crc0n0 cr0n0 used as capture register captures to cr0n0 at edge inverse to valid edge of ti0n0 pin cr0n1 used as capture register (c) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 0/1 0/1 0 1 0 3 prm0n 2 prm0n1 prm0n0 esn11 esn10 esn01 esn00 selects count clock (setting to 111 is prohibited.) specifies rising edge for pulse width detection setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 0/1 isel1n selcnt1 note be sure to clear the tmc0n1 bit to 0 when the to0n pin and ti0n0 pin are used alternately. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. for details, refer to 8.3 (1) 16-bit timer mode control register 0n (tmc0n) . 2. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 300 figure 8-17. timing of pulse width measurement by restarting (with rising edge specified) t (d1 + 1) t (d2 + 1) t d0 d0 d2 d1 d1 d2 0001h 0000h 0001h 0000h 0001h 0000h count clock tm0n count value ti0n0 pin input inttm0n1 value loaded to cr0n1 value loaded to cr0n0 remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 301 8.4.4 operation as external event counter setting procedure the basic operation setting procedure is as follows. <1> set the crc0n register (refer to figure 8-18 for the setting value). <2> set the count clock using the prm0n register and selcnt1 register. <3> set any value (except for 0000h) to the cr0n0 register. <4> set the tmc0n register: start operation (refer to figure 8-18 for the setting value). remarks 1. for the alternate-function pin (ti0n0) settings, refer to table 4-14 settings when port pins are used for alternate functions . 2. for inttm0n0 interrupt enable, refer to chapter 19 interrupt/exception processing function . the external event counter counts the number of clock pulses input to the ti0n0 pin from an external source by using the tm0n register. each time the valid edge specified by the prm0n regist er has been input, the tm0n r egister is incremented. when the count value of the tm0n regist er matches the value of the cr0n0 r egister, the tm0n register is cleared to 0000h and an interrupt request signal (inttm0n0) is generated. set the cr0n0 register to a value other than 0000 h (one-pulse count operation is not possible). the edge is specified by the prm0n.esn00 and prm0n.es n01 bits. the rising, falling, or both the rising and falling edges can be specified. the valid edge is detected through sampling at a count clock cycle of f xx /4, and the capture operation is not performed until the valid level is detected twice. as a re sult, noise with a short pulse width can be eliminated. caution the value of the cr0n0 a nd cr0n1 registers cannot be changed during time r count operation. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 302 figure 8-18. control register se ttings in external ev ent count mode (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr0n0 1 0/1 note 0 (b) capture/compare cont rol register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register 0/1 0/1 0 (c) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 0/1 0/1 0 1 0 3 prm0n 2 prm0n1 prm0n0 esn11 esn10 esn01 esn00 selects external clock specifies rising edge for external event count input setting invalid (setting to 10 is prohibited.) 01 1 0 isel1n selcnt1 note be sure to clear the tmc0n1 bit to 0 when the to0n pin and ti0n0 pin are used alternately. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the external event counter function. for details, refer to 8.3 (1) 16-bit timer mode control register 0n (tmc0n) and 8.3 (2) capture/compare c ontrol register 0n (crc0n) . 2. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 303 figure 8-19. configuration of external event counter 16-bit timer capture/compare register 0n0 (cr0n0) 16-bit timer counter 0n (tm0n) 16-bit timer capture/compare register 0n1 (cr0n1) selector ovf0n inttm0n0 count clock note fxx/4 ti0n0 valid edge internal bus noise eliminator match clear note set with the prm0n register and selcnt1 register. remark n = 0, 1 figure 8-20. timing of external event coun ter operation (with rising edge specified) 0000h 0001h 0002h 0003h 0000h 0001h 0002h 0003h 0004h 0005h n ? 1n n ti0n0 pin input tm0n count value cr0n0 inttm0n0 count start cautions 1. read the tm0n regi ster when reading the count value of the external event counter. 2. counting is not possible at the first valid edge after the externa l event count mode is entered. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 304 8.4.5 square-wave output operation setting procedure the basic operation setting procedure is as follows. <1> set the count clock using the prm0n register and selcnt1 register. <2> set the crc0n register (refer to figure 8-21 for the setting value). <3> set the toc0n register (refer to figure 8-21 for the setting value). <4> set any value (except for 0000h) to the cr0n0 register. <5> set the tmc0n register: start operation (refer to figure 8-21 for the setting value). remarks 1. for the alternate-function pin (to0n) settings, refer to table 4-14 settings when port pins are used for alternate functions . 2. for inttm0n0 interrupt enable, refer to chapter 19 interrupt/exception processing function . 16-bit timer/event counter 0n can be us ed to output a square wave with any fr equency at an interval specified by the count value set in advance to the cr0n0 register. by setting the toc0n.toe0n and toc0n.to c0n1 bits to 11, the out put status of the to0n pin is inverted at an interval set in advance to the cr0n0 register. in this way, a square wave of any frequency can be output. caution the value of the cr0n0 a nd cr0n1 registers cannot be changed during time r count operation. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 305 figure 8-21. control register setti ngs in square-wave output mode (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts upon match between tm0n and cr0n0 100 (b) capture/compare cont rol register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register 0/1 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 0 0 0 0/1 toc0n lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output inverts output upon match between tm0n and cr0n0 specifies initial value of to0n output f/f does not invert output upon match between tm0n and cr0n1 disables one-shot pulse output 0/1 1 1 (d) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 0/1 0/1 0/1 0/1 0 3 prm0n 2 prm0n1 prm0n0 esn11 esn10 esn01 esn00 selects count clock setting invalid (setting to 10 is prohibited.) setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 0/1 isel1n selcnt1 remarks 1. for details, refer to 8.3 (2) capture/compare c ontrol register 0n (crc0n) and 8.3 (3) 16-bit timer output control register 0n (toc0n) . 2. n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 306 figure 8-22. timing of square-wave output operation 0000h 0001h 0002h 0000h 0001h 0002h n ? 1n n 0000h n ? 1n count clock tm0n count value cr0n0 inttm0n0 to0n pin output remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 307 8.4.6 one-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti0n0 pin input). setting procedure the basic operation setting procedure is as follows. <1> set the count clock using the prm0n register and selcnt1 register. <2> set the crc0n register (refer to figures 8-23 and 8-25 for the setting value). <3> set the toc0n register (refer to figures 8-23 and 8-25 for the setting value). <4> set any value to the cr0n0 and cr0n1 registers. <5> set the tmc0n register: start operation (refer to figures 8-23 and 8-25 for the setting value). remarks 1. for the alternate-function pin (to0n) settings, refer to table 4-14 settings when port pins are used for alternate functions . 2. for inttm0n0 interrupt enable, refer to chapter 19 interrupt/exception processing function . (1) one-shot pulse output with software trigger a one-shot pulse can be output from the to0n pin by setting the tmc0n, crc0n, and toc0n registers as shown in figure 8-23, and by setting the toc0n.ospt0n bit to 1 by software. by setting the ospt0n bit to 1, 16-bit timer/event count er 0n is cleared and start ed, and its output becomes active at the count value (n) set in advance to the cr0n1 register. after that, the output becomes inactive at the count value (m) set in advance to the cr0n0 register note . even after the one-shot pulse has been output, 16-bit timer/ event counter 0n continues its operation. to stop 16-bit timer/event counter 0n, t he tmc0n.tmc0n3 and tmc0n.tmc0n2 bits must be cleared to 00. note the case where n < m is described here. when n > m, the output becomes active with the cr0n0 register and inactive with the cr0n1 register. cautions 1. do not set the ospt0n bit to 1 while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-shot pulse output is completed. 2. the value of the cr0n0 and cr0n1 regi sters cannot be change d during timer count operation. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 308 figure 8-23. control register settings for one- shot pulse output with software trigger (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00000 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n free-running timer mode 100 (b) capture/compare cont rol register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 0 1 1 0/1 toc0n lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output inverts output upon match between tm0n and cr0n0 specifies initial value of to0n output f/f inverts output upon match between tm0n and cr0n1 sets one-shot pulse output mode set to 1 for output 0/1 1 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 309 figure 8-23. control register settings for one- shot pulse output with software trigger (2/2) (d) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 0/1 0/1 0/1 0/1 0 3 prm0n 2 prm0n1 prm0n0 esn11 esn10 esn01 esn00 selects count clock setting invalid (setting to 10 is prohibited.) setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 0/1 isel1n selcnt1 caution do not set 0000h to the cr0n0 and cr0n1 registers. remarks 1. for details, refer to 8.3 (2) capture/compare c ontrol register 0n (crc0n) and 8.3 (3) 16-bit timer output control register 0n (toc0n) . 2. n = 0, 1 figure 8-24. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1m ? 1 0001h m + 1 m + 2 0000h count clock tm0n count cr0n1 set value cr0n0 set value ospt0n inttm0n1 inttm0n0 to0n pin output when tmc0n register is set to 04h caution 16-bit timer counter 0n starts operati ng as soon as a value other than 00 (operation stop mode) is set to the tmc0 n3 and tmc0n2 bits. remark n = 0, 1 n < m chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 310 (2) one-shot pulse output with external trigger a one-shot pulse can be output from the to0n pin by setting the tmc0n, crc0n, and toc0n registers as shown in figure 8-25, and by using the valid edg e of the ti0n0 pin as an external trigger. the valid edge of the ti0n0 pin is specified by the prm0n.esn00 and prm 0n.esn01 bits. the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti0n0 pin is detected, 16-bit timer/ev ent counter 0n is clear ed and started, and the output becomes active at the count value set in advance to the cr0n1 register. after that, the output becomes inactive at the count value set in advance to the cr0n0 register note . note the case where n < m is described here. when n > m, the output becomes active with the cr0n0 register and inactive with the cr0n1 register. cautions 1. even if the external trigger is gene rated again while the one-s hot pulse is output, it is ignored. 2. the value of the cr0n0 and cr0n1 regi sters cannot be change d during timer count operation. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 311 figure 8-25. control register settings for on e-shot pulse output with external trigger (with rising edge specified) (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 00001 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts at valid edge of ti0n0 pin 000 (b) capture/compare cont rol register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 00 1 1 0/1 toc0n lvr0n toc0n1 toe0n ospe0n ospt0n toc0n4 lvs0n enables to0n output inverts output upon match between tm0n and cr0n0 specifies initial value of to0n output f/f inverts output upon match between tm0n and cr0n1 sets one-shot pulse output mode 0/1 1 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 312 figure 8-25. control register settings for on e-shot pulse output with external trigger (with rising edge specified) (2/2) (d) prescaler mode register 0n (prm0n) and selector operation control register 1 (selcnt1) 0/1 0/1 0 1 0 3 prm0n 2 prm0n1 prm0n0 esn11 esn10 esn01 esn00 selects count clock (setting to 111 is prohibited.) specifies rising edge for pulse width detection. setting invalid (setting to 10 is prohibited.) 0 0/1 0/1 0/1 isel1n selcnt1 caution do not set the cr0n0 and cr0n1 registers to 0000h. remarks 1. for details, refer to 8.3 (2) capture/compare c ontrol register 0n (crc0n) and 8.3 (3) 16-bit timer output control register 0n (toc0n) . 2. n = 0, 1 figure 8-26. timing of one-shot pulse output operation with external trigger (wit h rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? 2m ? 1 0001h 0000h count clock tm0n count value cr0n1 set value cr0n0 set value ti0n0 pin input inttm0n1 inttm0n0 to0n pin output when tmc0n is set to 08h caution 16-bit timer/event counter 0n starts ope rating as soon as a value other than 00 (operation stop mode) is set to the tm c0n2 and tmc0n3 bits. remark n = 0, 1 n < m chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 313 8.4.7 cautions (1) alternate functions of ti0n0/to0n pins channel pin alternate function remarks ti000 p33/to00/tip00/top00 shares the pin with to00. ti001 p34/to00/tip01/top01 shares the pin with to00. p33/ti000/tip00/top00 tm00 to00 p34/ti001/tip01/top01 assigned to two pins, p33 and p34. ti010 p35/to01 shares the pin with to01. ti011 p50/kr0/rtp00 p32/asck0/adtrg tm01 to01 p35/ti010 assigned to two pins, p32 and p35. (a) for tm00 channel ? when using the output of to00 that functions alternately as p33, only a software trigger (toc00.ospt00 bit) can be used as the trigger in the one-shot pulse output mode. a p33/ti000 pin input signal cannot be used as the trigger since ti00 0 and to00 share a pin and are used alternately. a ti000 pin input signal can be used as the trigge r, however, when using the output of to00 that functions alternately as p34. ? when using the output of to00 that functions altern ately as p33, the timer output inversion operation using the valid edge of the ti000 pi n input cannot be performed. the valid edge cannot be input to the p33/ti000 pin since ti000 and to00 share a pin and ar e used alternately. set the tmc00.tmc001 bit to 0 in this event. the timer output inversion oper ation using the valid edge of t he ti000 pin input can be performed, however, when using the output of to 00 that functions alternately as p34. (b) for tm01 channel ? when using the output of to01 that functions alternately as p35, only a software trigger (toc01.ospt01 bit) can be used as the trigger in the one-shot pulse output mode. a p35/ti010 pin input signal cannot be used as the trigger since ti01 0 and to01 share a pin and are used alternately. a ti010 pin input signal can be used as the trigge r, however, when using the output of to01 that functions alternately as p32. ? when using the output of to01 that functions altern ately as p35, the timer output inversion operation using the valid edge of the ti010 pi n input cannot be performed. the valid edge cannot be input to the p35/ti010 pin since ti010 and to01 share a pin and ar e used alternately. set the tmc01.tmc011 bit to 0 in this event. the timer output inversion oper ation using the valid edge of t he ti010 pin input can be performed, however, when using the output of to 01 that functions alternately as p32. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 314 (2) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the count of the tm0n register is st arted asynchronously to the count pulse. figure 8-27. count start timing of tm0n register 0000h timer start 0001h 0002h 0003h 0004h count pulse tm0n count value remark n = 0, 1 (3) setting cr0n0 and cr0n1 register s (in the mode in which clear & start occurs upon match between tm0n register and cr0n0 register) set the cr0n0 and cr0n1 registers to a value other th an 0000h (when using these registers as external event counters, one-pulse count operation is not possible). remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 315 (4) data hold timing of capture register <1> if the valid edge of the ti0n0 pin is input while t he cr0n1 register is read, the cr0n1 register performs capture operation, but the read value at this time is not guarant eed. however, the interrupt request signal (inttm0n1) is generated as a result of detection of the valid edge. figure 8-28. data hold timing of capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm0n count value edge input inttm0n1 cr0n1 capture value capture read signal capture operation is performed but read value is not guaranteed capture operation remark n = 0, 1 <2> the values of the cr0n0 and cr0n1 registers are not guaranteed after 16-bit timer/event counter 0n has stopped. (5) setting valid edge before setting the valid edge of the ti0n0 pin, stop the timer operation by clear ing the tmc0n.tmc0n2 and tmc0n.tmc0n3 bits to 00. set the valid edge by using the prm0n.esn00 and prm0n.esn01 bits. remark n = 0, 1 (6) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is output, do not set the to c0n.ospt0n bit to 1. do not output the one-shot pulse again until the inttm0n0 signal, which occu rs upon match with the cr0n0 register, or the inttm0n1 signal, which occurs upon match with the cr0n1 register, occurs. remark n = 0, 1 (b) one-shot pulse output with external trigger if the external trigger occurs again while a one-shot pulse is output, it is ignored. chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 316 (7) operation of ovf0n flag (a) setting of ovf0n flag the tmc0n.ovf0n flag is set to 1 in the following case in addition to when the tm0n register overflows. select the mode in which clear & start occurs upon match between the tm0n r egister and the cr0n0 register. set the cr0n0 register to ffffh when the tm0n register is cleared from ffffh to 0000h upon match with the cr0n0 register figure 8-29. operation timing of ovf0n flag fffeh ffffh ffffh 0000h 0001h count pulse tm0n inttm0n0 ovf0n cr0n0 remark n = 0, 1 (b) clearing of ovf0n flag after the tm0n register overflows, clearing ovf0n fl ag is invalid and set (1) again even if the ovf0n flag is cleared (0) before the next count clock is c ounted (before the tm0n regi ster becomes 0001h). remark n = 0, 1 (8) timer operation (a) cr0n1 register capture even if the tm0n register is read, the read data cannot be captured into the cr0n1 register. (b) ti0n0, ti0n1 pin acknowledgment regardless of the cpu?s operation mode, if the time r is stopped, signals input to the ti0n0 and ti0n1 pins are not acknowledged. (c) one-shot pulse output one-shot pulse output operates norma lly in either the free-running timer mode or the mode in which clear & start occurs on the valid edge of the ti0n0 pin. because no overflow occurs in the mode in which clear & start occurs upon match between the tm0n register and the cr0n0 register, one- shot pulse output is not possible. remark n = 0, 1 chapter 8 16-bit timer/event counter 0 preliminary user?s manual u16895ej1v0ud 317 (9) capture operation (a) if valid edge of ti0n0 is specified for count clock if the valid edge of ti0n0 is specified for the count clo ck, the capture register t hat specified ti0n0 as the trigger does not operate normally. (b) if both rising and falling edges are selected for valid edge of ti0n0 if both the rising and falling edges are selected for t he valid edge of ti0n0, capture operation is not performed. (c) to ensure that signals from ti0n 1 and ti0n0 are correctly captured for the capture trigger to capture the signals from ti0n1 and ti0n0 correc tly, a pulse longer than two of the count clocks selected by the prm0n regi ster and selcnt1 register is required. (d) interrupt request input although a capture operation is per formed at the falling edge of the count clock, an interrupt request signal (inttm0n0, inttm0n1) is generated at t he rising edge of the next count clock. remark n = 0, 1 (10) compare operation when set to the compare mode, the cr0n0 and cr0n1 re gisters do not perform capt ure operation even if a capture trigger is input. caution the value of the cr0n0 re gister cannot be changed during ti mer operation. the value of the cr0n1 register cannot be cha nged during timer operation other than in the ppg output mode. to change the cr0n1 register in the ppg output mode, refer to 8.4.2 ppg output operation. remark n = 0, 1 (11) edge detection (a) sampling clock for noise elimination the sampling clock for noise elimination differs dep ending on whether the valid edge of ti0n0 is used for the count clock or as a capture trigger. in the former case, sampling is performed using f xx /4, and in the latter case, sampling is performed using the count clock selected by the prm0n register and selcnt1 register. the first capture operati on does not start until the valid edges are sampled and two valid levels are detected, thus eliminating noise with a short pulse width. remarks 1. f xx : main clock frequency 2. n = 0, 1 preliminary user?s manual u16895ej1v0ud 318 chapter 9 8-bit timer/event counter 5 in the v850es/kf1+, two channels of 8-bi t timer/event counter 5 are provided. 9.1 functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1). ? mode using 8-bit timer/event counter alone (individual mode) ? mode using cascade connection (16-bit resolution: cascade connection mode) these two modes are described below. (1) mode using 8-bit timer/event counter alone (i ndividual mode) 8-bit timer/event counter 5n operates as an 8-bit timer/event counter. the following functions can be used. ? interval timer ? external event counter ? square-wave output ? pwm output (2) mode using cascade connection (16-bi t resolution: cascade connection mode) 8-bit timer/event counter 5n operates as a 16-bit ti mer/event counter by c onnecting the tm50 and tm51 registers in cascade. the following functions can be used. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 319 9.2 configuration 8-bit timer/event counter 5n cons ists of the following hardware. table 9-1. configuration of 8-bit timer/event counter 5n item configuration timer registers 8-bit timer counters 50, 51 (tm50, tm51) 16-bit timer counter 5 (tm5): on ly when using cascade connection registers 8-bit timer compare registers 50, 51 (cr50, cr51) 16-bit timer compare register 5 (cr5 ): only when using cascade connection timer output to50, to51 control registers note timer clock selection regist ers 50, 51 (tcl50, tcl51) 8-bit timer mode control registers 50, 51 (tmc50, tmc51) 16-bit timer mode control register 5 (t mc5): only when using cascade connection note when using the functions of the ti5n and to5n pins, refer to table 4-14 settings when port pins are used for alternate functions . remark n = 0, 1 the block diagram of 8-bit timer/event counter 5n is shown below. figure 9-1. block diagram of 8-bit timer/event counter 5n ovf ti5n 3 tcl5n2 tcl5n1 tcl5n0 tce5n tmc5n6 tmc5n4 lvs5n lvr5n tmc5n1 toe5n to5n inttm5n s r q inv s r q match clear count clock note selector internal bus internal bus 8-bit timer mode control register 5n (tmc5n) 8-bit timer compare register 5n (cr5n) 8-bit timer counter 5n (tm5n) selector invert level mask circuit timer clock selection register 5n (tcl5n) selector selector note the count clock is set by the tcl5n register. remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 320 (1) 8-bit timer counter 5n (tm5n) the tm5n register is an 8-bit read-only re gister that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. through cascade connection, the tm5n registers can be used as a 16-bit timer. when using the tm50 register and the tm 51 register in cascade as a 16-bi t timer, these registers are read- only, in 16-bit units. therefore, read these registers twice and compare t he values, taking into consideration that the reading occurs during a count change. tm5n (n = 0, 1) 642 after reset: 00h r address: tm50 fffff5c0h, tm51 fffff5c1h 0 753 1 the count value is reset to 00h in the following cases. <1> reset <2> when the tmc5n.tce5n bit is cleared (0) <3> the values of the tm5n register and cr5n register match in the mode in which clear & start occurs on a match between the tm5n regist er and the cr5n register caution when connected in cascade, these registers become 0000h ev en when the tce50 bit in the lowest timer (tm50) is cleared. remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 321 (2) 8-bit timer compare register 5n (cr5n) the cr5n register can be read and written in 8-bit units. in a mode other than the pwm mode, the value set to the cr5n register is always compared to the count value of the tm5n register, and if the two values match, an interrupt request signal (inttm5n) is generated. in the pwm mode, tm5n register overfl ow causes the to5n pin output to chan ge to the active level, and when the values of the tm5n register and the cr5n register match, the to5n pi n output changes to the inactive level. the value of the cr5n register can be set in the range of 00h to ffh. when using the tm50 register and tm51 register in ca scade as a 16-bit timer, the cr50 register and cr51 register operate as 16-bit timer compare register 5 (cr5 ). the counter value and register value are compared in 16-bit lengths, and if they match, an inte rrupt request signal (inttm50) is generated. cr5n (n = 0, 1) 642 after reset: 00h r/w address: cr50 fffff5c2h, cr51 fffff5c3h 0 753 1 cautions 1. in the mode in which clear & start occurs upon a match of the tm5n register and cr5n register (tmc5n.tmc5n6 bit = 0), do not writ e a different value to the cr5n register during the count operation. 2. in the pwm mode, set the cr5n register re write interval to thr ee or more count clocks (clock selected with the tcl5n register). 3. before changing the value of the cr5n re gister when using a cascade connection, be sure to stop the timer operation. remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 322 9.3 registers the following two registers are used to co ntrol 8-bit timer/event counter 5n. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) remark to use the functions of the ti5n and to5n pins, refer to table 4-14 settings when port pins are used for alternate functions . (1) timer clock selection register 5n (tcl5n) the tcl5n register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the ti5n pin input. the tcl5n register can be read or written in 8-bit units. after reset, this register is cleared to 00h. falling edge of ti5n rising edge of ti5n f xx f xx /2 f xx /4 f xx /64 f xx /256 inttm010 count clock selection note tcl5n2 0 0 0 0 1 1 1 1 tcl5n1 0 0 1 1 0 0 1 1 tcl5n0 0 1 0 1 0 1 0 1 20 mhz 10 mhz ? ? setting prohibited 100 ns 200 ns 3.2 s 12.8 s ? ? ? 100 ns 200 ns 0.4 s 6.4 s 25.6 s ? clock f xx 0 tcl5n (n = 0, 1) 0 0 0 0 tcl5n2 tcl5n1 tcl5n0 after reset: 00h r/w address: tcl50 fffff5c4h, tcl51 fffff5c5h 76 54 32 1 0 note when the internal clock is selected, set so as to satisfy the following conditions. regc = v dd = 4.0 to 5.5 v: count clock 10 mhz regc = capacity, v dd = 4.0 to 5.5 v: count clock 5 mhz regc = v dd = 2.7 to 4.0 v: count clock 5 mhz caution before overwriting the tcl5n register with different data, stop the timer operation. remark when the tm5n register is connected in casc ade, the tcl51 register settings are invalid. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 323 (2) 8-bit timer mode control register 5n (tmc5n) the tmc5n register performs the following six settings. ? controls counting by the tm5n register ? selects the operation m ode of the tm5n register ? selects the individual mode or cascade connection mode ? sets the status of t he timer output flip-flop ? controls the timer output flip-flop or selects the active level in the pwm (free-running timer) mode ? controls timer output the tmc5n register can be read or written in 8-bit or 1-bit units. after reset, this register is cleared to 00h. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 324 tce5n counting is disabled after the counter is cleared to 0 (counter disabled) start count operation tce5n 0 1 control of count operation of 8-bit timer/event counter 5n tmc5n (n = 0, 1) tmc5n6 0 tmc514 note lvs5n lvr5n tmc5n1 toe5n mode in which clear & start occurs on match between tm5n register and cr5n register pwm (free-running timer) mode tmc5n6 0 1 selection of operation mode of 8-bit timer/event counter 5n individual mode cascade connection mode (connected with 8-bit timer/event counter 50) tmc514 0 1 selection of individual mode or cascade connection mode for 8-bit timer/event counter 51 unchanged reset timer output f/f to 0 set timer output f/f to 1 setting prohibited lvs5n 0 0 1 1 setting of status of timer output f/f lvr5n 0 1 0 1 after reset: 00h r/w address: tmc50 fffff5c6h, tmc51 fffff5c7h disable inversion operation enable inversion operation high active low active tmc5n1 0 1 other than pwm (free-running timer) mode (tmc5n6 bit = 0) controls timer f/f pwm (free-running timer) mode (tmc5n6 bit = 1) selects active level disable output (to5n pin is low level) enable output toe5n 0 1 timer output control <7> 6 5 4 3 2 1 <0> note bit 4 of the tmc50 register is fixed to 0. cautions 1. because the to51 and ti51 pins are al ternate functions of the same pin, only one can be used at one time. 2. the lvs5n and lvr5n bit settings are val id in modes other than the pwm mode. 3. do not set <1> to <4> below at the same time. set as follows. <1> set the tmc5n1 , tmc5n6, and tmc514 note bits: setting of operation mode <2> set the toe5n bit for timer output enable: timer output enable <3> set the lvs5n and lvr5n bits (caution 2): setting of timer output f/f <4> set the tce5n bit remarks 1. in the pwm mode, the pwm output is set to the inactive level by the tce5n bit = 0. 2. when the lvs5n and lvr5n bits are read, 0 is read. 3. the values of the tmc5n6, l vs5n, lvr5n, tmc5n1, and toe 5n bits are reflected to the to5n output regardless of the tce5n bit value. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 325 9.4 operation 9.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer t hat repeatedly generates interrupt s at the interval of the count value preset in the cr 5n register. if the count value in the tm5n register matches the value set in the cr5n register, the value of the tm5n register is cleared to 00h and counting is continued, and at the same time, an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation and selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n regist er (tmc5n register = 0000xx00b, : don?t care). <2> when the tmc5n.tce5n bit is set to 1, the count operation starts. <3> when the values of the tm5n regi ster and cr5n register match, the inttm5n signal is generated (tm5n register is cleared to 00h). <4> then, the inttm5n signal is repe atedly generated at the same interval . to stop counting, set the tce5n bit = 0. interval time = (n + 1) t: n = 00h to ffh caution during interval timer operation, do not rewrite the value of the cr5n register. remark n = 0, 1 figure 9-2. timing of interval timer operation (1/2) basic operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm5n count value cr5n tce5n inttm5n count start remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 326 figure 9-2. timing of interval timer operation (2/2) when cr5n register = 00h t interval time 00h 00h 00h 00h 00h count clock tm5n count value cr5n tce5n inttm5n remark n = 0, 1 when cr5n register = ffh t 01h 00h feh ffh 00h feh ffh 00h ffh ffh ffh count clock tm5n count value cr5n tce5n inttm5n interval time interrupt acknowledgment interrupt acknowledgment remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 327 9.4.2 operation as external event counter the external event counter c ounts the number of clock pulses input to the ti5n pin from an external source by using the tm5n register. each time the valid edge specified by the tcl5n register is input to the ti5n pin, the tm5n register is incremented. either the rising edge or the falling e dge can be specified as the valid edge. when the count value of the tm5n regist er matches the value of the cr5n regi ster, the tm5n register is cleared to 0 and an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? tcl5n register: selects the ti5n pin input edge. falling edge of ti5n pin tcl5n register = 00h rising edge of ti5n pin tcl5n register = 01h ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n register , disables timer output f/f inversion operation, and disables timer output. (tmc5n register = 0000xx00b, : don?t care) ? for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, the counter co unts the number of pulses in put from the ti5n pin. <3> when the values of the tm5n regi ster and cr5n register match, the inttm5n signal is generated (tm5n register is cleared to 00h). <4> then, the inttm5n signal is generat ed each time the values of t he tm5n register and cr5n register match. inttm5n signal is generated when the valid edge is input to the ti5n pin n + 1 times: n = 00h to ffh caution during external event counter operation, do not rewrite the value of the cr5n register. remark n = 0, 1 figure 9-3. timing of external event coun ter operation (with rising edge specified) 00h 01h 02h 03h 04h 05h n ? 1n n 00h 01h 02h 03h ti5n cr5n inttm5n tce5n tm5n count value count start remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 328 9.4.3 square-wave output operation a square wave with any frequency can be output at an interval determined by the value preset in the cr5n register. by setting the tmc5n.toe5n bit to 1, the output status of the to5n pin is inverted at an interval determined by the count value preset in the cr 5n register. in this way, a square wave of any frequency can be output (duty = 50%) (n = 0, 1). setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n register, sets initial value of timer output, enables timer output f/f inversion operation, and enables timer output. (tmc5n register = 00001011b or 00000111b) ? for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, counting starts. <3> when the values of the tm5n register and cr5n regi ster match, the timer output f/f is inverted. moreover, the inttm5n signal is generated and the tm5n register is cleared to 00h. <4> then, the timer output f/f is inve rted during the same interval and a s quare wave is output from the to5n pin. frequency = 1/2t(n + 1): n = 00h to ffh caution do not rewrite the value of the cr5n register during square-wave output. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 329 figure 9-4. timing of square-wave output operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm5n count value cr5n to5n note tce5n inttm5n count start note the initial value of the to5n pin output can be set using the tmc5n.lvs5n and tmc5n.lvr5n bits. remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 330 9.4.4 8-bit pwm output operation by setting the tmc5n.tmc5n6 bit to 1, 8-bit ti mer/event counter 5n performs pwm output. pulses with a duty factor determined by the value set in the cr5n register are out put from the to5n pin. set the width of the active level of the pwm pulse in t he cr5n register. the active level can be selected using the tmc5n.tmc5n1 bit. the count clock can be select ed using the tcl5n register. pwm output can be enabled/disabled by the tmc5n.toe5n bit. caution the cr5n register rewrite interval must be three or more operation clocks (set by the tcl5n register). use method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation, se lects pwm mode, and leave timer output f/f unchanged, sets active level, and enables timer output. (tmc5n register = 01000001b or 01000011b) ? for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, counting starts. pwm output operation <1> when counting starts, pwm output (output from the to5n pin) outputs the inactive level until an overflow occurs. <2> when an overflow occurs, the active level set by setting method <1> is output. the active level is output until the value of the cr5n register and the count value of the tm5n register match. an interrupt request signal (inttm5n) is generated. <3> when the value of the cr5n register and the count value of the tm5n register match, the inactive level is output and continues to be output until an overflow occurs again. <4> then, steps <2> and <3> are repeat ed until counting is stopped. <5> when counting is stopped by clearing tce5n bit to 0, pwm output becomes inactive. cycle = 256t, active level width = nt, duty = n/256: n = 00h to ffh remarks 1. n = 0, 1 2. for the detailed timing, refer to figure 9-5 timing of pwm output operation and figure 9-6 timing of operation b ased on cr5n register transitions . chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 331 (a) basic operation of pwm output figure 9-5. timing of pwm output operation basic operation (active level = h) 00h n + 1 n n 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h active level inactive level active level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = 00h 00h n + 1 n + 2 n 00h 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = ffh 00h n + 1 n + 2 n ffh 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level inactive level active level active level count clock tm5n count value cr5n tce5n inttm5n to5n t remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 332 (b) operation based on cr5n register transitions figure 9-6. timing of operation b ased on cr5n register transitions when the value of the cr5n register changes from n to m before the rising edge of the ffh clock the value of the cr5n register is transferred at the overflow that occurs immediately after. n n + 1 n + 2 m n <1> cr5n transition (n m) m m + 1 m + 2 m m + 1 m + 2 ffh 02h 00h 01h ffh 02h 00h 01h count clock tm5n count value cr5n tce5n h inttm5n to5n <2> t when the value of the cr5n register changes from n to m after the rising edge of the ffh clock the value of the cr5n register is transferred at the second overflow. n n + 1 n + 2 n nn <1> cr5n transition (n m) m n + 1 n + 2 m m + 1 m + 2 ffh 03h 02h 00h 01h ffh 02h 00h 01h count clock tm5n count value cr5n tce5n h inttm5n to5n <2> t caution in the case of read from the cr5n register between <1> and <2>, the value that is actually used differs (read value: m; actu al value of cr5n register: n). remark n = 0, 1 chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 333 9.4.5 operation as inter val timer (16 bits) the 16-bit resolution timer/event counter mode is se lected by setting the tmc51.tmc514 bit to 1. 8-bit timer/event counter 5n operates as an interval time r by repeatedly generating inte rrupts using the count value preset in 16-bit timer compare register 5 (cr5) as the interval. setting method <1> set each register. ? tcl50 register: selects the count clock (t) (the tcl51 register does not need to be set in cascade connection) ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 registers: selects the mode in which clear & start occurs on a match between tm5 register and cr5 register ( : don?t care) tmc50 register = 0000xx00b tmc51 register = 0001xx00b <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 to start the count operation. <3> when the values of the tm5 r egister and cr5 register connected in cascade match, the inttm50 signal is generated (the tm5 register is cleared to 0000h). <4> the inttm50 signal is then generated repeatedly at the same interval. interval time = (n + 1) t: n = 0000h to ffffh cautions 1. to write using 8-bit access during cascade connection, set th e tce51 bit to 1 at operation start and then set the tce50 bit to 1. when operation is stopped, clear the tce50 bit to 0 and then clear the tce51 bit to 0. 2. during cascade connection, ti50 pin input, to50 pin ou tput, and the inttm50 signal are used. do not use ti51 pin input, to 51 pin output, and the inttm51 signal; mask them instead (for details, refer to chapter 19 interrupt/exception processing function). clear the lvs51, lvr51, tmc511, and toe51 bits to 0. 3. do not change the value of the cr5 register during timer operation. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 334 figure 9-7 shows a timing example of the cascade connection mode with 16-bit resolution. figure 9-7. cascade connection mode with 16-bit resolution 00h n + 1 01h 00h ffh 00h 01h ffh 00h ffh m ? 1 01h 00h 00h na 01h 00h 02h m 00h 00h b n n m interval time operation enabled, count start interrupt occurrence, counter cleared operation stopped count clock tm50 count value tm51 count value tce51 inttm50 cr51 tce50 cr50 t chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 335 9.4.6 operation as external event counter (16 bits) the 16-bit resolution timer/event counter mode is selected by setting the tmc51.tmc514 bit to 1. the external event counter counts the number of clock pulse s input to the ti50 pin from an external source using 16-bit timer counter 5 (tm5). setting method <1> set each register. ? tcl50 register: selects the ti50 pin input edge. (the tcl51 register does not have to be set during cascade connection.) falling edge of ti50 pin tcl50 register = 00h rising edge of ti50 pin tcl50 register = 01h ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 registers: stops count operation, selects the cl ear & start mode entered on a match between the tm5 register and cr5 regi ster, disables timer output f/f inversion, and disables timer output. ( : don?t care) tmc50 register = 0000xx00b tmc51 register = 0001xx00b ? for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions. <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 and count the number of pulses input from the ti50 pin. <3> when the values of the tm5 r egister and cr5 register connected in cascade match, the inttm50 signal is generated (the tm5 register is cleared to 0000h). <4> the inttm50 signal is then generated each time the va lues of the tm5 register and cr5 register match. inttm50 signal is generated when the valid edge is input to the ti50 pin n + 1 times: n = 0000h to ffffh cautions 1. during external event counter opera tion, do not rewrite the value of the cr5n register. 2. to write using 8-bit access during cascade connection, set the tce51 bit to 1 and then set the tce50 bit to 1. when operation is stopped, clear the tce50 bit to 0 and then clear the tce51 bit to 0 (n = 0, 1). 3. during cascade connection, ti50 pin input and the inttm 50 signal are used. do not use ti51 pin input, to51 pin ou tput, and the inttm51 signal; mask them instead (for details, refer to chapter 19 interrup t/exception processing function). clear the lvs51, lvr51, tmc 511, and toe51 bits to 0. 4. do not change the value of the cr5 regi ster during external event counter operation. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 336 9.4.7 square-wave output operat ion (16-bit resolution) the 16-bit resolution timer/event counter mode is se lected by setting the tmc51.tmc514 bit to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (cr5). setting method <1> set each register. ? tcl50 register: selects the count clock (t) (the tcl51 register does not have to be set in cascade connection) ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 registers: stops count operation, se lects the mode in which clear & start occurs on a match between the tm5 register and cr5 register. lvs50 lvr50 timer output f/f status settings 1 0 high-level output 0 1 low-level output enables timer output f/f inversion, and enables timer output. tmc50 register = 00001011b or 00000111b tmc51 register = 00010000b ? for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions. <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 to start the count operation. <3> when the values of the tm5 regi ster and the cr5 register connected in cascade match, the to50 timer output f/f is inverted. moreover, the inttm50 sign al is generated and the tm 5 register is cleared to 0000h. <4> then, the timer output f/f is inve rted during the same interval and a s quare wave is output from the to50 pin. frequency = 1/2t(n + 1): n = 0000h to ffffh caution do not write a different value to the cr5 register during operation. chapter 9 8-bit timer/event counter 5 preliminary user?s manual u16895ej1v0ud 337 9.4.8 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the tm5n register is started a synchronously to the count pulse. figure 9-8. count start timing of tm5n register 00h timer start 01h 02h 03h 04h count pulse tm5n count value remark n = 0, 1 preliminary user?s manual u16895ej1v0ud 338 chapter 10 8-bit timer h in the v850es/kf1+, two channels of 8-bit timer h are provided. 10.1 functions 8-bit timer hn has the following functions. ? interval timer ? pwm output ? square wave output ? carrier generator mode remark n = 0, 1 10.2 configuration 8-bit timer hn consists of the following hardware. table 10-1. configuration of 8-bit timer hn item configuration timer registers 8-bit ti mer counter hn: 1 each registers 8-bit timer h compare register n0 (cmpn0): 1 each 8-bit timer h compare register n1 (cmpn1): 1 each timer outputs 1 each (tohn pin) control registers note 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) note to use the tohn pin function, refer to table 4-14 settings when port pins are used for alternate functions . remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 339 the block diagram of 8-bit timer hn is shown below. figure 10-1. block diag ram of 8-bit timer hn match selector internal bus tmhen ckshn2 ckshn1 ckshn0 tmmdn1tmmdn0 tolevn toenn decoder 8-bit timer h compare register n0 (cmpn0) reload/ interrupt control tohn inttmhn inttm5n selector rmc n nrzb n f xx f xx /2 f xx /2 2 f xx /2 4 f xx /2 6 f xx /2 10 f r /2 11 interrupt generator output controller level inversion nrz n 1 0 f/f r 8-bit timer counter hn carrier generator mode signal pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register n1 (cmpn1) 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 340 (1) 8-bit timer h compare register n0 (cmpn0) the cmpn0 register can be read or written in 8-bit units. after reset, cmpn0 is cleared to 00h. cmpn0 (n = 0, 1) after reset: 00h r/w address: cmp00 fffff582h, cmp10 fffff592h 76 54 32 1 0 caution rewriting the cmpn0 register during timer count operation is prohibited. (2) 8-bit timer h compare register n1 (cmpn1) the cmpn1 register can be read or written in 8-bit units. after reset, cmpn1 is cleared to 00h. cmpn1 (n = 0, 1) after reset: 00h r/w address: cmp01 fffff583h, cmp11 fffff593h 76 54 32 1 0 the cmpn1 register can be rewritt en during timer count operation. in the carrier generator mode, after the cmpn1 register is set, if the count value of 8-bit timer counter hn and the set value of the cmpn1 register match, an interrupt request signal (in ttmhn) is generated. at the same time, the value of 8-bit timer counter hn is cleared to 00h. if the set value of the cmpn1 register is rewritten dur ing timer operation, the reload timing is when the count value of 8-bit timer counter hn and the set value of the cmpn1 register match. if the transfer timing and write to the cmpn1 register by software conflict, transfer is not performed. caution in the pwm output mode a nd carrier generator mode, be su re to set the cmpn1 register when starting the timer count operation (t mhmdn.tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register). chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 341 10.3 registers the registers that control 8-bit timer hn are as follows. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register n (tmcycn) remarks 1. to use the tohn pin function, refer to table 4-14 settings when port pins are used for alternate functions . 2. n = 0, 1 (1) 8-bit timer h mode register n (tmhmdn) the tmhmdn register controls the mode of 8-bit timer hn. the tmhmdn register can be read or written in 8-bit or 1-bit units. after reset, tmhmdn is cleared to 00h. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 342 (a) 8-bit timer h mode register 0 (tmhmd0) tmhe0 stop timer count operation (8-bit timer counter h0 = 00h) enable timer count operation (counting starts when clock is input) tmhe0 0 1 8-bit timer h0 operation enable tmhmd0 cksh02 cksh01 cksh00 tmmd01 tmmd00 tolev0 toen0 after reset: 00h r/w address: fffff580h f xx f xx /2 f xx /4 f xx /16 f xx /64 f xx /1024 cksh02 0 0 0 0 1 1 cksh01 0 0 1 1 0 0 cksh00 0 1 0 1 0 1 setting prohibited 125 ns 250 ns 1 s 4 s 64 s selection of count clock count clock note interval timer mode carrier generator mode pwm output mode setting prohibited tmmd01 0 0 1 1 tmmd00 0 1 0 1 8-bit timer h0 operation mode other than above low level high level tolev0 0 1 timer output level control (default) disable output enable output toen0 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 <1> <0> setting prohibited f xx = 10.0 mhz setting prohibited 100 ns 200 ns 800 ns 1.6 s 51.2 s f xx = 20 mhz 100 ns 200 ns 400 ns 1.6 s 6.4 s 102.4 s note set so as to satisfy the following conditions. v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = capacity: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz cautions 1. when the tmhe0 bit = 1, setting bits other than those of the tmhmd0 register is prohibited. 2. in the pwm output mode and carrier generator mode, be sure to set the cmp01 register when starting the timer count ope ration (tmhe0 bit = 1) after the timer count operation was stopped (tmhe0 bit = 0) (be sure to set again even if setting the same value to th e cmp01 register). 3. when using the carrier generator mode , set 8-bit timer h0 count clock frequency to six times 8-bit timer/event counter 50 count clock frequency or higher. chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 343 (b) 8-bit timer h mode register 1 (tmhmd1) tmhe1 stop timer count operation (8-bit timer counter h1 = 00h) enable timer count operation (counting starts when clock is input) tmhe1 0 1 8-bit timer h1 operation enable tmhmd1 cksh12 cksh11 cksh10 tmmd11 tmmd10 tolev1 toen1 after reset: 00h r/w address: fffff590h f xx f xx /2 f xx /4 f xx /16 f xx /64 cksh12 0 0 0 0 1 1 cksh11 0 0 1 1 0 0 cksh10 0 1 0 1 0 1 setting prohibited 125 ns 250 ns 1 s 4 s selection of count clock count clock note interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 8-bit timer h1 operation mode f r /2048 setting prohibited other than above low level high level tolev1 0 1 timer output level control (default) disable output enable output toen1 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 <1> <0> setting prohibited 100 ns 200 ns 800 ns 1.6 s f xx = 20.0 mhz f xx = 10.0 mhz 100 ns 200 ns 400 ns 1.6 s 6.4 s note set so as to satisfy the following conditions. v dd = regc = 4.0 to 5.5 v: count clock 10 mhz v dd = 4.0 to 5.5 v, regc = capacity: count clock 5 mhz v dd = regc = 2.7 to 4.0 v: count clock 5 mhz cautions 1. when the tmhe1 bit = 1, setting bits other than those of the tmhmd1 register is prohibited. 2. in the pwm output mode and carrier generator mode, be sure to set the cmp11 register when starting the timer count ope ration (tmhe1 bit = 1) after the timer count operation was stopped (tmhe1 bit = 0) (be sure to set again even if setting the same value to th e cmp11 register). 3. when using the carrier generator mode , set 8-bit timer h1 count clock frequency to six times 8-bit timer/event counter 51 count clock frequency or higher. chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 344 (2) 8-bit timer h carrier cont rol register n (tmcycn) this register controls the 8-bit timer hn remote control output and carrier pulse output status. the tmcycn register can be read or written in 8-bit or 1-bit units, but the nrzn bit is a read-only bit. after reset, tmcycn is cleared to 00h. 0 tmcycn (n = 0, 1) 0 0 0 0 rmcn nrzbn nrzn after reset: 00h r/w address: tmcyc0 fffff581h, tmcyc1 fffff591h low-level output high-level output low-level output carrier pulse output rmcn 0 0 1 1 nrzbn 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enable status nrzn 0 1 carrier pulse output status flag 76 54 32 1<0> chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 345 10.4 operation 10.4.1 operation as interval timer/square wave output when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. the cmpn1 register cannot be used in the interval timer mode. even if the cmpn1 register is set, this has no effect on the timer output because matches between 8-bit timer counter hn and the cmpn1 regi ster are not detected. a square wave of the desired frequency (duty = 50%) is out put from the tohn pin, by setting the tmhmdn.toenn bit to 1. (1) usage method the inttmhn signal is repeatedly generated in the same interval. <1> set each register. figure 10-2. register settings in interval timer mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 0 sets timer output sets timer output level inversion sets interval timer mode selects count clock (f cnt ) stops count operation 0 0/1 0/1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register settings ? compare value (n) <2> when the tmhen bit is set to 1, counting starts. <3> when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, the inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. interval time = (n + 1)/f cnt <4> then, the inttmhn signal is generated in the same interval. to stop the count operation, clear the tmhen bit to 0. chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 346 (2) timing chart the timing in the interval timer mode is as follows. figure 10-3. timing of interval timer/ square wave output operation (1/2) basic operation 00h count clock count start 8-bit timer counter hn count value cmpn0 tmhen inttmhn tohn 01h n clear clear n 00h 01h n 00h 01h 00h <1> <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <3> interval time <1> when the tmhen bit is set to 1, the count operation is enabled. the count clock starts counting no more than one clock after operation has been enabled. <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, the value of 8-bit timer counter hn is cleared, the tohn output level is inverted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive when the tmhen bit is cleared to 0 during 8-bit timer hn operation. if the level is al ready inactive, it remains unchanged. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 347 figure 10-3. timing of interval timer/ square wave output operation (2/2) operation when cmpn0 register = ffh 00h count clock count start cmpn0 tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time 8-bit timer counter hn count value operation when cmpn0 register = 00h count clock count start cmpn0 tmhen inttmhn tohn 00h 00h interval time 8-bit timer counter hn count value remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 348 10.4.2 pwm output mode operation in the pwm output mode, a pulse of any duty and cycle can be output. the cmpn0 register controls the time r output (tohn) cycle. rewriting the cmpn0 register during timer operation is prohibited. the cmpn1 register controls the time r output (tohn) duty. the cmpn1 r egister can be rewritten during timer operation. the operation in the pwm out put mode is as follows. after timer counting starts, when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, the tohn output becomes active and 8-bit timer count er hn is cleared to 00h. when the count value of 8-bit timer counter hn and the set value of the cmpn1 re gister match, tohn output becomes inactive. (1) usage method in the pwm output mode, a pulse of any duty and cycle can be output. <1> set each register. figure 10-4. register settings in pwm output mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 1 enables timer output sets timer output level inversion selects pwm output mode selects count clock (f cnt ) stops count operation 0 0/1 1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register setting ? compare value (n): sets cycle (iii) cmpn1 register setting ? compare value (m): sets duty remarks 1. n = 0, 1 2. 00h cmpn1 (m) < cmpn0 (n) ffh <2> when the tmhen bit is set to 1, counting starts. chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 349 <3> after the count operation is enabled, the first compare register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, 8-bit timer counter hn is cleared, an interrupt request si gnal (inttmhn) is generated, and the tohn output becomes active. at the same time, the register t hat is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <4> when the count value of 8-bit timer counter hn and the set value of the cmpn1 register match, the tohn output becomes inactive, and at the same time the register that is compared with 8-bit timer counter hn changes from the cmpn1 r egister to the cmpn0 register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> a pulse of any duty can be obtained throug h the repetition of steps <3> and <4> above. <6> to stop the count operation, clear the tmhen bit to 0. designating the set value of the cmpn0 register as (n ), the set value of the cm pn1 register as (m), and the count clock frequency as f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n + 1)/f cnt duty = inactive width: active width = (m + 1) : (n + 1) cautions 1. in the pwm output mode, three opera ting clocks (signal selected by ckshn0 to ckshn2 bits) are required for actual transfer of the new value to the register after the cmpn1 register has been rewritten. 2. be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register). chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 350 (2) timing chart the operation timing in the pwm out put mode is as follows. caution the set value (m) of the cm pn1 register and the set value (n ) of the cmpn0 register must always be set within th e following range. 00h cmpn1 (m) < cmpn0 (n) ffh figure 10-5. operation timing in pwm output mode (1/4) basic operation count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h <1> <3> <2> cmpn1 <4> a5h 01h 8-bit timer counter hn count value <1> when the tmhen bit is set to 1, counting starts. at this time tohn output st ays inactive (tolevn bit = 0). <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, the tohn output level is inverted, 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 r egister match, the tohn output level is inverted. at this time, the value of 8-bit timer counter hn is not cleared and the inttmhn signal is not output. <4> when the tmhen bit is cleared to 0 during 8-bit timer hn operation, the inttmhn signal and tohn output becomes inactive. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 351 figure 10-5. operation timing in pwm output mode (2/4) operation when cmpn0 register = ffh, cmpn1 register = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmpn1 ffh 00h 8-bit timer counter hn count value operation when cmpn0 register = ffh, cmpn1 register = feh count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmpn1 ffh feh 8-bit timer counter hn count value remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 352 figure 10-5. operation timing in pwm output mode (3/4) operation when cmpn0 register = 01h, cmpn1 register = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmpn1 00h 8-bit timer counter hn count value remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 353 figure 10-5. operation timing in pwm output mode (4/4) operation based on cmpn1 register tr ansitions (cmpn1 register = 01h 03h, cmpn0 register = a5h) count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h <1> <4> <3> <2> cmpn1 <6> <5> 01h a5h 03h 01h (03h) <2>' 8-bit timer counter hn count value <1> when the tmhen bit is set to 1, counting starts. at this time, the tohn output remains inactive (tolevn bit = 0). <2> the set value of the cmpn1 register can be changed during count operati on. this operation is asynchronous to the count clock. <3> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 register match, 8-bit timer counter hn is cleared, the tohn output becomes ac tive, and the inttmhn signal is generated. <4> even if the value of the cmpn1 register is chang ed, that value is latched and not transferred to the register. when the count value of 8-bit timer counter hn and the set value of the cmpn1 register prior to the change match, the changed value is transferred to the cmpn1 register and the value of the cmpn1 register is changed (<2>?). however, three or more count clocks are required fr om the time the value of the cmpn1 register is changed until it is transferred to the register. even if a match signal is generated within three count clocks, the changed valu e cannot be transferred to the register. <5> when the count value of 8-bit timer counter hn ma tches the changed set value of the cmpn1 register, the tohn output becomes inactive. 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <6> when the tmhen bit is cleared to 0 during 8-bit timer hn operation, the inttmhn signal and tohn output become inactive. chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 354 10.4.3 carrier genera tor mode operation the carrier clock generated by 8-bit timer hn is output using the cycle set with 8-bit timer/event counter 5n. in the carrier generator mode, 8-bit timer/ event counter 5n is used to control the extent to wh ich the carrier pulse of 8-bit timer hn is output, and the carrier pulse is output from the tohn output. (1) carrier generation in the carrier generator mode, the cmpn0 register gener ates a waveform with the low-level width of the carrier pulse and the cmpn1 register generates a waveform with the high-level width of the carrier pulse. during 8-bit timer hn operation, the cmpn1 register can be rewritten, but rewriting of the cmpn0 register is prohibited. (2) carrier output control carrier output control is performed wit h the interrupt request signal (inttm 5n) of 8-bit timer/event counter 5n and the tmcycn.nrzbn and tmcycn.rmcn bits. t he output relationships are as follows. rmcn bit nrzbn bit output 0 0 low level output 0 1 high level output 1 0 low level output 1 1 carrier pulse output remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 355 to control carrier pulse output during count operati on, the tmcycn.nrzn and tm cycn.nrzbn bits have a master and slave bit configuration. the nrzn bit is read-only while the nrzbn bit can be read and written. the inttm5n signal is synchronized with the 8-bit timer hn clock and output as the inttm5hn signal. the inttm5hn signal becomes the data transfer signal of the nrzn bit and the value of the nrzbn bit is transferred to the nrzn bit. the transfer timing from the nrzbn bit to the nrzn bit is as follows. figure 10-6. transfer timing 8-bit timer hn count clock tmhen inttm5n inttm5hn nrzn nrzbn rmcn 1 1 1 0 00 <1> <2> <1> the inttm5n signal is synchronized with the count clock of 8-bit timer hn and is output as the inttm5hn signal. <2> the value of the nrzbn bit is transferred to the nrzn bit at the second clock from the rising edge of the inttm5hn signal. cautions 1. do not rewrite the nrzbn bit again until at least the second cl ock after it has been rewritten, or else transfer from the nrzbn bit to the nrzn bit is not guaranteed. 2. when using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. an interrupt o ccurs at a different timing when it is used in other than the carrier generator mode. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 356 (3) usage method any carrier clock can be output from the tohn pin. <1> set each register. figure 10-7. register settings in carrier generator mode ? 8-bit timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 enables timer output sets timer output level inversion selects carrier generator mode selects count clock (f cnt ) stops count operation 1 0/1 1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 ? cmpn0 register: compare value ? cmpn1 register: compare value ? tmcycn register: rmcn = 1 ... re mote control output enable bit nrzbn = 0/1 ... carrier output enable bit ? tcl5n, tmc5n registers: refer to 9.3 registers . remark n = 0, 1 <2> when the tmhen bit is set to 1, 8-bit timer hn count operation starts. <3> when the tmc5n.tce5n bit is set to 1, 8-bi t timer/event counter 5n count operation starts. <4> after the count operation is enabled, the first compare register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, the inttmhn signal is generated, 8-bit timer counter hn is cleared, and at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <5> when the count value of 8-bit timer counter hn and the set value of the cmpn1 register match, the inttmhn signal is generated, 8-bit timer counter hn is cleared, and at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. <6> the carrier clock is obtained through t he repetition of steps <4> and <5> above. <7> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. this signal becomes the data transfer signal of the nrzbn bit and the value of t he nrzbn bit is transferred to the nrzn bit. <8> when the nrzn bit becomes high level, the carri er clock is output from the tohn pin. <9> any carrier clock can be obtained through the repetiti on of the above steps. to stop the count operation, clear the tmhen bit to 0. chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 357 designating the set value of the cmpn0 register as (n ), the set value of the cm pn1 register as (m), and the count clock frequency as f cnt , the carrier clock output cycle and duty are as follows. carrier clock output cycle = (n + m + 2)/f cnt duty = high level width: carrier clock out put width = (m + 1) : (n + m + 2) caution be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation w as stopped (tmhen bit = 0) (b e sure to set again even if setting the same value to the cmpn1 register). (4) timing chart the carrier output control timing is as follows. cautions 1. set the values of the cmpn0 and cm pn1 registers in the range of 01h to ffh. 2. in the carrier generator mode, thr ee operating clocks (signal selected by the tmhmdn.ckshn0 to tmhmdn.cks hn2 bits) are required for actual transfer of the new value to the register after the cmpn 1 register has been rewritten. 3. be sure to perform the tmcycn.rmcn bit se tting before the start of the count operation. 4. when using the carrier generator mode, set the 8-bit timer hn c ount clock frequency to six times the 8-bit timer/ event counter 5n count clock frequency or higher. chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 358 figure 10-8. carrier ge nerator mode (1/3) operation when cmpn0 register = n, cmpn1 register = n is set cmpn0 cmpn1 tmhen inttmhn carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 5n count clock tm5n count value cr5n tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l l inttm5hn <1> <2> <3> <4> <5> <6> <7> 8-bit timer hn count clock 8-bit timer counter hn count value <1> when the tmhen bit = 0 and the tce5n bit = 0, the operation of 8-bit timer hn is stopped. <2> when the tmhen bit is set to 1, 8-bit timer hn starts c ounting. the carrier clock is maintained inactive at this time. <3> when the count value of 8-bit timer counter hn and th e set value of the cmpn0 r egister match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register t hat is compared with 8-bit timer counter hn changes from the cm pn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is invert ed, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a duty of 50% is generated through the repetition of steps <3> and <4>. <5> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the inttm5hn signal becomes the data transfer signal of the nrzbn bit, and the va lue of the nrzbn bit is transferred to the nrzn bit. <7> the tohn output is made low level by clearing the nrzn bit to 0. remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 359 figure 10-8. carrier ge nerator mode (2/3) operation when cmpn0 register = n, cmpn1 register = m is set n l cmpn0 cmpn1 tmhen inttmhn carrier clock tm5n count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m cr5n tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l inttm5hn <1> <2> <3> <4> <5> <6> <7> 8-bit timer 5n count clock 8-bit timer hn count clock 8-bit timer counter hn count value <1> when the tmhen bit = 0 and the tce5n bit = 0, the operation of 8-bit timer hn is stopped. <2> when the tmhen bit is set to 1, 8-bit timer hn starts c ounting. the carrier clock is maintained inactive at this time. <3> when the count value of 8-bit timer counter hn and th e set value of the cmpn0 r egister match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register t hat is compared with 8-bit timer counter hn changes from the cm pn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is invert ed, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a fixed duty (other than 50%) is generated through the repetiti on of steps <3> and <4>. <5> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the carrier is output from the rising edge of t he first carrier clock by setting the nrzn bit to 1. <7> by clearing the nrzn bit to 0, the tohn output is also maintained high level while the carrier clock is high level, and does not change to low level (the high leve l width of the carrier waveform is guaranteed through steps <6> and <7>). remark n = 0, 1 chapter 10 8-bit timer h preliminary user?s manual u16895ej1v0ud 360 figure 10-8. carrier ge nerator mode (3/3) operation based on cmpn1 register transitions 8-bit timer hn count clock cmpn0 tmhen inttmhn carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>' <4> <3> <2> cmpn1 <5> m n l m (l) 8-bit timer counter hn count value <1> when the tmhen bit is set to 1, counting starts. the carrier clock is maintained inactive at this time. <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, 8-bit timer counter hn is cleared to 00h and the inttmhn signal is output. <3> the cmpn1 register can be rewri tten during 8-bit timer hn operation, but the changed value (l) is latched. the value of the cmpn1 register is changed when the co unt value of 8-bit timer counter hn and the value of the cmpn1 register prior to the change (m) match (<3>?). <4> when the count value of 8-bit timer counter hn and the value (m) of the cmpn1 re gister match, the inttmhn signal is output, the carrier signal is inverted, and 8-bit timer counter hn is cleared to 00h. <5> the timing at which the count value of 8-bit timer c ounter hn and the set value of the cmpn1 register match again is the changed value (l). remark n = 0, 1 preliminary user?s manual u16895ej1v0ud 361 chapter 11 interval timer, watch timer the v850es/kf1+ includes interval timer brg and a watch timer. interval timer brg can also be used as the source clock of the watch timer. the watch timer can also be used as interval timer wt. two interval timer channels and one watch timer channel can be used at the same time. 11.1 interval timer brg 11.1.1 functions interval timer brg has the following functions. ? interval timer brg: an interrupt request si gnal (intbrg) is generated at a specified interval. ? generation of count clock for watch timer: when the main clock is used as the count clock for the watch timer, a count clock (f brg ) is generated. 11.1.2 configuration the following shows the block diagram of interval timer brg. figure 11-1. block diagra m of interval timer brg f x f x /8 f x /4 f x /2 f x bgcs0 bgcs1 todis bgce 3-bit prescaler 8-bit counter clear match f bgcs count clock for watch timer intbrg prsm register prscm register 2 internal bus f brg clock control output control selector remark f x : main clock oscillation frequency f bgcs : interval timer brg count clock frequency f brg : watch timer count clock frequency intbrg: interval timer brg interrupt request signal chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 362 (1) clock control the clock control controls supp ly/stop of the operation clock (f x ) of interval timer brg. (2) 3-bit prescaler the 3-bit prescaler divides f x to generate f x /2, f x /4, and f x /8. (3) selector the selector selects the count clock (f bgcs ) for interval timer brg from f x , f x /2, f x /4, and f x /8. (4) 8-bit counter the 8-bit counter counts the count clock (f bgcs ). (5) output control the output control controls supply of the count clock (f brg ) for the watch timer. (6) prscm register the prscm register is an 8-bit compare re gister that sets the interval time. (7) prsm register the prsm register controls the oper ation of interval timer brg, the selector, and clock supply to the watch timer. chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 363 11.1.3 registers interval timer brg includes the following registers. (1) interval timer brg mode register (prsm) prsm controls the operation of interval timer brg, se lection of count clock, and clock supply to the watch timer. this register can be read or written in 8-bit or 1-bit units. after reset, prsm is cleared to 00h. 0 prsm 0 0 bgce 0 todis bgcs1 bgcs0 operation stopped, 8-bit counter cleared to 01h operate bgce 0 1 control of interval timer operation f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs1 0 0 1 1 bgcs0 0 1 0 1 selection of input clock (f bgcs ) note after reset: 00h r/w address: fffff8b0h clock for watch timer supplied clock for watch timer not supplied todis 0 1 control of clock supply for watch timer 10 mhz 100 ns 200 ns 400 ns 800 ns < > note set these bits so that the fo llowing conditions are satisfied. v dd = 4.0 to 5.5 v: f bgcs chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 364 (2) interval timer brg compare register (prscm) prscm is an 8-bit compare register. this register can be read or written in 8-bit units. after reset, prscm is cleared to 00h. prscm7 prscm prscm6 prscm5 prscm4 prscm3 prscm2 prscm1 prscm0 after reset: 00h r/w address: fffff8b1h caution do not rewrite the prscm regi ster while interval timer brg is operating (prsm.bgce bit = 1). set the prscm register before setting (1) the bgce bit. chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 365 11.1.4 operation (1) operation of interval timer brg set the count clock by using the prsm.bgcs1 and prsm .bgcs0 bits and the 8-bit compare value by using the prscm register. when the prsm.bgce bit is set (1), interval timer brg starts operating. each time the count value of the 8-bit counter and the set value in the prscm register match, an interrupt request signal (intbrg) is generated. at the same time, the 8-bit counter is cleared to 00h and counting is continued. the interval time can be obtained from the following equation. interval time = 2 m chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 366 11.2 watch timer 11.2.1 functions the watch timer has the following functions. ? watch timer: an interrupt request signal (intwt) is generated at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. ? interval timer: an interrupt request signal (i ntwti) is generated at the preset time interval. the watch timer and interval timer functions can be used at the same time. 11.2.2 configuration the following shows the block di agram of the watch timer. figure 11-2. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 selector selector selector selector remark f brg : frequency of count clock from interval timer brg f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt request signal intwti: interval timer interrupt request signal chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 367 (1) 11-bit prescaler the 11-bit prescaler generates a clock of f w /2 4 to f w /2 11 by dividing f w . (2) 5-bit counter the 5-bit counter generates the watch timer interru pt request signal (intwt) at intervals of 2 4 /f w , 2 5 /f w , 2 13 /f w , or 2 14 /f w by counting f w or f w /2 9 . (3) selectors the watch timer has the following four selectors. ? selector that selects the main clo ck (the clock from interval timer brg (f brg ) or the subclock (f xt )) as the clock for the watch timer. ? selector that selects f w or f w /2 9 as the count clock frequency of the 5-bit counter ? selector that selects 2 4 /f w or 2 13 /f w , or 2 5 /f w or 2 14 /f w as the intwt signal generation time interval. ? selector that selects the generation time interval of the interval timer wt inte rrupt request signal (intwti) from 2 4 /f w to 2 11 /f w . (4) 8-bit counter the 8-bit counter counts the count clock (f bgcs ). (5) wtm register the wtm register is an 8-bit register that controls the operation of the watch timer/interval timer wt and sets the interval of interrupt request signal generation. 11.2.3 register the watch timer includes the following register. (1) watch timer operation mode register (wtm) this register enables or disables the count clock and operation of the watch ti mer, sets the interval time of the 11-bit prescaler, controls the operation of the 5-bit counter, and sets the time of watch timer interrupt request signal (intwt) generation. the wtm register can be read or written in 8-bit or 1-bit units. after reset, wtm is cleared to 00h. chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 368 wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.91 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.3 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval time of prescaler wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < > 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clear after operation stops start wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stop operation (clear both prescaler and 5-bit counter) enable operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits wh ile both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply when f w = 32.768 khz chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 369 11.2.4 operation (1) operation as watch timer the watch timer generates an interrupt re quest at fixed time intervals. the watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 khz). the count operation starts when the wtm.wtm0 and wtm. wtm1 bits are set to 11. when these bits are cleared to 00, the 11-bit prescaler and 5-bit count er are cleared and the count operation stops. the 5-bit counter can be cleared to synchronize the time by clearing the wtm1 bit to 0 when the watch timer and interval timer wt operate simultaneously. at this ti me, an error of up to 15.6 ms may occur in the watch timer, but interval timer wt is not affected. (2) operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (intwti) at intervals specified by a count value set in advance. the interval time can be selected by the wtm.wtm4 to wtm.wtm7 bits. table 11-1. interval ti me of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4 1/f w 488 s (operating at f w = f xt = 32.768 khz) 0 0 0 1 2 5 1/f w 977 s (operating at f w = f xt = 32.768 khz) 0 0 1 0 2 6 1/f w 1.95 ms (operating at f w = f xt = 32.768 khz) 0 0 1 1 2 7 1/f w 3.91 ms (operating at f w = f xt = 32.768 khz) 0 1 0 0 2 8 1/f w 7.81 ms (operating at f w = f xt = 32.768 khz) 0 1 0 1 2 9 1/f w 15.6 ms (operating at f w = f xt = 32.768 khz) 0 1 1 0 2 10 1/f w 31.3 ms (operating at f w = f xt = 32.768 khz) 0 1 1 1 2 11 1/f w 62.5 ms (operating at f w = f xt = 32.768 khz) 1 0 0 0 2 4 1/f w 488 s (operating at f w = f brg = 32.768 khz) 1 0 0 1 2 5 1/f w 977 s (operating at f w = f brg = 32.768 khz) 1 0 1 0 2 6 1/f w 1.95 ms (operating at f w = f brg = 32.768 khz) 1 0 1 1 2 7 1/f w 3.91 ms (operating at f w = f brg = 32.768 khz) 1 1 0 0 2 8 1/f w 7.81 ms (operating at f w = f brg = 32.768 khz) 1 1 0 1 2 9 1/f w 15.6 ms (operating at f w = f brg = 32.768 khz) 1 1 1 0 2 10 1/f w 31.3 ms (operating at f w = f brg = 32.768 khz) 1 1 1 1 2 11 1/f w 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 370 figure 11-3. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remarks 1. assuming that the interrupt time of the watch timer is set to 0.5 seconds. 2. f w : watch timer clock frequency values in parentheses apply when count clock f w = 32.768 khz. n: number of interval timer wt operations 11.3 cautions (1) operation as watch timer some time is required before the first watch timer inte rrupt request signal (intwt) is generated after operation is enabled (wtm.wtm1 and wtm.wtm0 bits = 11). figure 11-4. example of generation of watc h timer interrupt request signal (intwt) (when interrupt period = 0.5 s) it takes 0.515625 (max.) seconds for the first intwt signal to be generated (2 9 1/32768 = 0.015625 (max.) seconds longer). an intwt signal is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt chapter 11 interval timer, watch timer preliminary user?s manual u16895ej1v0ud 371 (2) when watch timer and interval timer brg operate simultaneously when using the subclock as the count clock for the watch ti mer, the interval time of interval timer brg can be set to any value. changing the interval time does not a ffect the watch timer (before changing the interval time, stop operation). when using the main clock as the count clock for the watch timer, set the interval time of interval timer brg to approximately 65,536 hz. do not change this value. (3) when interval timer brg and inter val timer wt operate simultaneously when using the subclock as the count clock for interval ti mer wt, the interval times of interval timers brg and wt can be set to any values. they can also be cha nged later (before changing the value, stop operation). when using the main clock as the count clock for interval timer wt, the interval time of interval timer brg can be set to any value, but cannot be changed later (it can be changed only when interval timer wt stops operation). the interval time of interval timer wt can be set to 2 5 to 2 12 of the set value of interval timer brg. it can also be changed later. (4) when watch timer and interval timer wt operate simultaneously the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer wt (clear (0) the wtm.wtm0 bit) while the watch timer is operating. if the wtm0 bit is set (1) after it had been cleared (0), the watch timer will have a discrepancy of up to 0.5 or 0.25 seconds. (5) when watch timer, interval timer brg, and interval time r wt operate simultaneously when using the subclock as the count clock for the watch timer, the interval times of interval timers brg and wt can be set to any values. the interval time of interval timer brg can be changed later (before changing the value, stop operation). when using the main clock as the count clock for the watch timer, set the interval time of interval timer brg to approximately 65,536 khz. it cannot be c hanged later. the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer brg (clear (0) the prsm.bgce bit) or interval timer wt (clear (0) the wtm.wtm0 bit) while the watch timer is operating. preliminary user?s manual u16895ej1v0ud 372 chapter 12 watchdog timer functions 12.1 watchdog timer 1 12.1.1 functions watchdog timer 1 has the following operation modes. ? watchdog timer ? interval timer the following functions are realized fr om the above-listed operation modes. ? generation of non-maskable interrupt request si gnal (intwdt1) upon overflow of watchdog timer 1 note ? generation of system reset signal (wdtres1 ) upon overflow of watchdog timer 1 ? generation of maskable interrupt request signal (intwdtm1) upon overflow of interval timer note for non-maskable interrupt servicing due to non-mask able interrupt request signal (intwdt1, intwdt2), refer to 19.10 cautions . remark select whether to use watchdog timer 1 in the watchdog timer 1 mode or the interval timer mode with the wdtm1 register. chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 373 figure 12-1. block diagra m of watchdog timer 1 wdtm14 wdtm13 run1 2 intwdtm1 wdtres1 3 wdcs1 wdcs0 wdcs2 f xw /2 21 f xw /2 15 f xw /2 16 f xw /2 17 f xw /2 18 f xw /2 19 f xw /2 14 f xw /2 13 intwdt1 f xw internal bus watchdog timer mode register 1 (wdtm1) watchdog timer clock selection register (wdcs) output controller prescaler clear selector remark intwdtm1: request signal for maskable interrupt through watchdog timer 1 overflow intwdt1: request signal for non-maskable inte rrupt through watchdog timer 1 overflow wdtres1: reset signal through watchdog timer 1 overflow f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 374 12.1.2 configuration watchdog timer 1 consists of the following hardware. table 12-1. configuration of watchdog timer 1 item configuration control registers watchdog timer clock select ion register (wdcs) watchdog timer mode register 1 (wdtm1) 12.1.3 registers the registers that control watchdo g timer 1 are as follows. ? watchdog timer clock selection register (wdcs) ? watchdog timer mode register 1 (wdtm1) (1) watchdog timer clock selection register (wdcs) this register sets the overflow time of watchdog timer 1 and the interval timer. the wdcs register can be read or wri tten in 8-bit or 1-bit units. after reset, wdcs is cleared to 00h. 0 wdcs 0 0 0 0 wdcs2 wdcs1 wdcs0 2 13 /f xw 2 14 /f xw 2 15 /f xw 2 16 /f xw 2 17 /f xw 2 18 /f xw 2 19 /f xw 2 21 /f xw wdcs2 0 0 0 0 1 1 1 1 overflow time of watchdog timer 1/interval timer wdcs1 0 0 1 1 0 0 1 1 wdcs0 0 1 0 1 0 1 0 1 4 mhz 10 mhz 5 mhz 2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.2 ms 52.43 ms 209.7 ms f xw after reset: 00h r/w address: fffff6c1h remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 375 (2) watchdog timer mode register 1 (wdtm1) this register sets the watchdog timer 1 operati on mode and enables/disables count operations. this register is a special register that c an be written only in a special sequence (refer to 3.4.7 special registers ). the wdtm1 register can be read or written in 8-bit or 1-bit units. after reset, wdtm1 is cleared to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm1 register using an access method that causes a wait. for details, refer to 3.4.8 (2). run1 stop counting clear counter and start counting run1 0 1 selection of operation mode of watchdog timer 1 note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (upon overflow, maskable interrupt intwdtm1 is generated.) watchdog timer mode 1 note 3 (upon overflow, non-maskable interrupt intwdt1 is generated.) watchdog timer mode 2 (upon overflow, reset operation wdtres1 is started.) wdtm14 0 0 1 1 wdtm13 0 1 0 1 selection of operation mode of watchdog timer 1 note 2 < > notes 1. once the run1 bit is set (to 1), it c annot be cleared (to 0) by software. therefore, when counti ng is started, it cannot be stopped except by reset. 2. once the wdtm13 and wdtm14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only by reset. 3. for non-maskable interrupt servicing due to non -maskable interrupt request signal (intwdt1), refer to 19.10 cautions . chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 376 12.1.4 operation (1) operation as watchdog timer 1 watchdog timer 1 operation to detect a program loop is selected by setting the wdtm1.wdtm14 bit to 1. the count clock (program loop detection time interv al) of watchdog timer 1 can be selected using the wdcs.wdcs0 to wdcs.wdcs2 bits. the count operation is started by setting the wdtm1.run1 bit to 1. when, after the count operation is st arted, the run1 bit is again set to 1 within the set program loop detection time interval, watchdog timer 1 is cleared and the count operation starts again. if the program loop detection time is exceeded without run 1 bit being set to 1, a reset signal (wdtres1) or a non-maskable interrupt request signal (intwdt1 ) is generated depending on the value of the wdtm1.wdtm13 bit. the count operation of watchdog timer 1 stops in t he stop mode and idle mode. set the run1 bit to 1 before the stop mode or idle mode is entered in order to clear watchdog timer 1. because watchdog timer 1 operates in the halt mode, make sure that an overflow will not occur during halt. cautions 1. when the subclock is selected for the cpu cl ock, the count operation of watchdog timer 1 is stopped (the value of watc hdog timer 1 is maintained). 2. for non-maskable interrupt servicing due to the intwdt1 signal, refer to 19.10 cautions. table 12-2. program loop detect ion time of watchdog timer 1 program loop detection time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.277 ms 1.683 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 377 (2) operation as interval timer watchdog timer 1 can be made to operate as an interval ti mer that repeatedly generates interrupts using the count value set in advance as the interval, by clearing the wdtm1.wdtm14 bit to 0. when watchdog timer 1 operates as an interval time r, the interrupt mask flag (wdtmk) and priority specification flags (wdtpr0 to wdtpr2) of the wdti c register are valid and maskable interrupt request signals (intwdtm1) can be generated. the default priority of the intwdtm1 signal is set to the highest level among the maskable interrupt request signals. the interval timer continues to operate in the halt mode, but it stops operating in the stop mode and the idle mode. cautions 1. once the wdtm14 bit is set to 1 (thereby selecting the watc hdog timer 1 mode), the interval timer mode is not entered as long as reset is not performed. 2. when the subclock is sel ected for the cpu clock, the count operation of the watchdog timer 1 stops (the value of the wa tchdog timer is maintained). table 12-3. interval ti me of interval timer interval time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.277 ms 1.638 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 378 12.2 watchdog timer 2 12.2.1 functions watchdog timer 2 has the following functions. ? default start watchdog timer note 1 reset mode: reset operation upon overflow of watchdog timer 2 (generation of wdtres2 signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note 2 ? input selectable from ring-osc clock and subclock as the source clock notes 1. watchdog timer 2 automatically starts in t he reset mode following reset release. when watchdog timer 2 is not used, either stop its operation before reset is executed through this function, or clear once watchdog timer 2 and stop it within the next interval time. also, write to the wdtm2 register for verifi cation purposes only once, even if the default settings (reset mode, interval time: f xx /2 25 ) need not be changed. 2. for non-maskable interrupt servicing due to a non -maskable interrupt request signal (intwdt2), refer to 19.10 cautions . figure 12-2. block diagra m of watchdog timer 2 f r /8 clock input controller output controller wdtres2 (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f r /2 12 to f r /2 19 or f xt /2 9 to f xt /2 16 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear remark f r : ring-osc clock frequency f xt : subclock frequency intwdt2: non-maskable interrupt request signal through watchdog timer 2 wdtres2: watchdog timer 2 reset signal chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 379 12.2.2 configuration watchdog timer 2 consists of the following hardware. table 12-4. configuration of watchdog timer 2 item configuration control registers watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) 12.2.3 registers (1) watchdog timer mode register 2 (wdtm2) this register sets the overflow time and operation clock of watchdog timer 2. the wdtm2 register can be read or writt en in 8-bit units. this register c an be read any number of times, but it can be written only once following reset release. after reset, wdtm2 is set to 67h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm2 register using an access method that causes a wait. for details, refer to 3.4.8 (2). 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2) reset mode (generation of wdtres2) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. to stop the operation of watchdog ti mer 2, write ?1fh? to the wdtm2 register. 2. for details about bits wdcs0 to wdcs4, refer to table 12-5 watchdog timer 2 clock selection. 3. if the wdtm2 register is written twice afte r a reset, an overflow signal is forcibly output. chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 380 table 12-5. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected clock program loop detection time 0 0 0 0 0 2 12 /f r 17.1 ms (f r = 240 khz (typ.)) 0 0 0 0 1 2 13 /f r 34.1 ms (f r = 240 khz (typ.)) 0 0 0 1 0 2 14 /f r 68.2 ms (f r = 240 khz (typ.)) 0 0 0 1 1 2 15 /f r 136.5 ms (f r = 240 khz (typ.)) 0 0 1 0 0 2 16 /f r 273.1 ms (f r = 240 khz (typ.)) 0 0 1 0 1 2 17 /f r 546.1 ms (f r = 240 khz (typ.)) 0 0 1 1 0 2 18 /f r 1092.3 ms (f r = 240 khz (typ.)) 0 0 1 1 1 2 19 /f r 2184.5 ms (f r = 240 khz (typ.)) 0 1 0 0 0 2 9 /f xt 15.625 ms (f xt = 32.768 khz) 0 1 0 0 1 2 10 /f xt 31.25 ms (f xt = 32.768 khz) 0 1 0 1 0 2 11 /f xt 62.5 ms (f xt = 32.768 khz) 0 1 0 1 1 2 12 /f xt 125 ms (f xt = 32.768 khz) 0 1 1 0 0 2 13 /f xt 250 ms (f xt = 32.768 khz) 0 1 1 0 1 2 14 /f xt 500 ms (f xt = 32.768 khz) 0 1 1 1 0 2 15 /f xt 1000 ms (f xt = 32.768 khz) 0 1 1 1 1 2 16 /f xt 2000 ms (f xt = 32.768 khz) 1 operation stopped (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cl eared and counting restarted by writin g ?ach? to the wdte register. the wdte register can be read or written in 8-bit units. after reset, wdte is set to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other th an ?ach? is written to the wdte register, an overflow signal is forcibly output. 2. when a 1-bit memory manipulation instru ction is executed for the wdte register, an overflow signal is forcibly output. 3. the read value of the wdte register is a lways ?9ah? (value that differs from written value ?ach?). chapter 12 watchdog timer functions preliminary user?s manual u16895ej1v0ud 381 12.2.4 operation watchdog timer 2 automatically starts in t he reset mode following reset release. the wdtm2 register can be written to only once following reset through byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm 2 register using 8-bit memory manipulation instructions. after this is done, the operation of watchdog timer 2 cannot be stopped. the watchdog timer 2 program loop detection time in terval can be selected by the wdtm2.wdcs24 to wdtm2.wdcs20 bits. writing ach to the wdte register clears the counter of watchdog timer 2 and starts the count operation again. after the count operat ion starts, write ach to the wdte r egister within the set program loop detection time interval. if the program loop detection time is exceeded without a ch being written to the wdte register, a reset signal (wdtres2) or non-maskable interrupt request signal (i ntwdt2) is generated depending on the set value of the wdtm2.wdm21 and wdtm2.wdm20 bits. to not use watchdog timer 2, writ e 1fh to the wdtm2 register. for non-maskable interrupt servicing when the non -maskable interrupt request mode is set, refer to 19.10 cautions . because watchdog timer 2 operates in the halt/idle/stop mode, exercise care that the timer does not overflow in the halt/idle/stop mode. preliminary user?s manual u16895ej1v0ud 382 chapter 13 real-time output function (rto) 13.1 function the real-time output function (rto) transfers preset data to the rtbl0 and rtbh0 registers, and then transfers this data with hardware to an external device via the r eal-time output latches, upon occurr ence of a timer interrupt. the pins through which the data is output to an external device constitute a port called a real-time output port. because rto can output signal without jitter, it is suitable for controlling a stepping motor. in the v850es/kf1+, a 6-bit real-time output port channel is provided. the real-time output port can be se t in the port mode or real-time output port mode in 1-bit units. the block diagram of rto is shown below. figure 13-1. block diagram of rto real-time buffer register 0h (rtbh0) real-time output latch 0h selector inttm000 inttm50 inttm51 real-time output latch 0l rtpoe0 rtpeg0 byte0 extr0 real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 real-time output port mode register 0 (rtpm0) 4 2 2 4 internal bus real-time buffer register 0l (rtbl0) rtpout04, rtpout05 rtpout00 to rtpout03 chapter 13 real-time output function (rto) preliminary user?s manual u16895ej1v0ud 383 13.2 configuration rto consists of the following hardware. table 13-1. configuration of rto item configuration registers real-time output buffe r register 0 (rtbl0, rtbh0) control registers real-time output port mode register 0 (rtpm0) real-time output port control register 0 (rtpc0) (1) real-time output buffer register 0 (rtbl0, rtbh0) rtbl0 and rtbh0 are 4-bit registers t hat hold output data in advance. these registers are mapped to independent addresses in the peripheral i/o register area. they can be read or written in 8-bit or 1-bit units. if an operation mode of 4 bits 1 channel or 2 bits 1 channel is specified (rtpc0.byte0 bit = 0), data can be individually set to the rtbl0 and rtbh0 registers. the data of both these r egisters can be read at once by specifying the address of ei ther of these registers. if an operation mode of 6 bits 1 channel is specified (byte0 bit = 1), 8-bit data can be set to both the rtbl0 and rtbh0 registers by writing the da ta to either of these registers. moreover, the data of both these registers can be read at once by specifying t he address of either of these registers. table 13-2 shows the operation when the rt bl0 and rtbh0 register s are manipulated. 0 rtbl0 rtbh0 0 rtbh05 rtbh04 rtbl03 rtbl02 rtbl01 rtbl00 after reset: 00h r/w address: rtbl0 fffff6e0h, rtbh0 fffff6e2h cautions 1. when writing to bits 6 and 7 of the rtbh0 register, always write 0. 2. when the main clock is stopped and the cpu is operating on the subclock, do not access the rtbl0 and rtbh0 registers using an access method that causes a wait. fo r details, refer to 3.4.8 (2). table 13-2. operation during manipul ation of rtbl0 and rtbh0 registers read write note operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl0 rtbh0 rtbl0 invalid rtbl0 4 bits 1 channel, 2 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 invalid rtbl0 rtbh0 rtbl0 rtbh0 rtbl0 6 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 rtbl0 note after setting the real-time output port, set output data to the rtbl0 and rtbh0 registers by the time a real- time output trigger is generated. chapter 13 real-time output function (rto) preliminary user?s manual u16895ej1v0ud 384 13.3 registers rto is controlled using the foll owing two types of registers. ? real-time output port mode register 0 (rtpm0) ? real-time output port control register 0 (rtpc0) (1) real-time output port mode register 0 (rtpm0) this register selects the real-time output port mode or port mode in 1-bit units. the rtpm0 register can be read or written in 8-bit or 1-bit units. after reset, rtpm0 is cleared to 00h. 0 rtpm0m 0 1 real-time output disabled real-time output enabled control of real-time output port (m = 0 to 5) rtpm0 0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 after reset: 00h r/w address: fffff6e4h cautions 1. to reflect real-time output signa ls (rtpout00 to rtpout05) to the pins (rtp00 to rtp05), set them to the r eal-time output port with the pmc5 and pfc5 registers. 2. by enabling real-time output operation (rtpc0.rtpoe0 bit = 1), the bits specified as real-time outpu t enabled perform real-time output, and the bits specified as real-time out put disabled output 0. 3. if real-time output is disabled (r tpoe0 bit = 0), real-time output signals (rtpout00 to rtpout05) all output 0, regardless of the rtpm0 register setting. chapter 13 real-time output function (rto) preliminary user?s manual u16895ej1v0ud 385 (2) real-time output port control register 0 (rtpc0) this register sets the operation mode and ou tput trigger of the real-time output port. the relationship between the operation mo de and output trigger of the real -time output port is as shown in table 13-3. the rtpc0 register can be read or written in 8-bit or 1-bit units. after reset, rtpc0 is cleared to 00h. rtpoe0 disables operation note 2 enables operation rtpoe0 0 1 control of real-time output operation rtpc0 rtpeg0 byte0 extr0 note 1 00 0 0 falling edge note 3 rising edge rtpeg0 0 1 valid edge of inttm000 signal 4 bits 1 channel, 2 bits 1 channel 6 bits 1 channel byte0 0 1 specification of channel configuration for real-time output after reset: 00h r/w address: fffff6e5h < > notes 1. for the extr0 bit, refer to table 13-3 . 2. when real-time output operation is dis abled (rtpoe0 bit = 0), real-time output signals (rtpout00 to rtpout05) all output 0. 3. the inttm000 signal is output for 1 clock of the count clock selected with 16-bit timer/event counter 00. caution perform the settings for the rtpeg0, byte0, and extr0 bits only when the rtpoe0 bit = 0. table 13-3. operation modes and output triggers of real-time output port byte0 extr0 operation mode rtbh0 (rtp 04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttm51 inttm50 0 1 4 bits 1 channel, 2 bits 1 channel inttm50 inttm000 0 inttm50 1 1 6 bits 1 channel inttm000 chapter 13 real-time output function (rto) preliminary user?s manual u16895ej1v0ud 386 13.4 operation if the real-time output operation is enabled by setting the rtpc0.rtpoe0 bi t to 1, the data of the rtbh0 and rtbl0 registers is transferred to the real-time output latch in synchronizati on with the generation of the selected transfer trigger (set by the rtpc0.extr0 and rtpc0.byte0 bits). of the trans ferred data, only the data of the bits specified as real-time output enabled by the rtpm0 register is output from bi ts rtpout00 to rtpo ut05. the bits specified as real-time output disabled by the rtpm0 register output 0. if the real-time output operatio n is disabled by clearing the rtpoe0 bi t to 0, the rtpout00 to rtpout05 signals output 0 regardless of the setti ng of the rtpm0 register. figure 13-2. example of operation timing of rto0 (when extr0 and byte0 bits = 00) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttm51 (internal) inttm50 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by inttm51 interrupt request signal (write to rtbh0 register) b: software processing by inttm50 interrupt request signal (write to rtbl0 register) remark for the operation during standby, refer to chapter 21 standby function . chapter 13 real-time output function (rto) preliminary user?s manual u16895ej1v0ud 387 13.5 usage (1) disable real-time output. clear the rtpc0.rtpoe0 bit to 0. (2) perform initializa tion as follows. ? specify the real-time output port m ode or port mode in 1-bit units. set the rtpm0 register. ? channel configuration: select the trigger and valid edge. set the rtpc0.extr0, rtpc0.byt e0, and rtpc0.rtpeg0 bits. ? set the initial values to the rtbh0 and rtbl0 registers note 1 . (3) enable real-time output. set the rtpoe0 bit to 1. (4) set the next output value to the rtbh0 and rtbl0 registers by the time the selected transfer trigger is generated note 2 . (5) set the next real-time output value to the rtbh0 and rtbl0 regi sters through interrupt servicing corresponding to the selected trigger. notes 1. if write to the rtbh0 and rtbl0 registers is per formed when the rtpoe0 bit = 0, that value is transferred to real-time output latches 0h and 0l, respectively. 2. even if write is performed to t he rtbh0 and rtbl0 registers when th e rtpoe0 bit = 1, data transfer to real-time output latches 0h and 0l is not performed. caution to reflect the real-time out put signals (rtpout00 to rtpout05) to the pi ns, set the real-time output ports (rtp00 to rtp05) with the pmc5 and pfc5 registers. 13.6 cautions (1) prevent the following conflicts by software. ? conflict between real-time output disable/enable s witching (rtpoe0 bit) and selected real-time output trigger ? conflict between write to the rtbh0 and rtbl0 regist ers in the real-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoe0 bit = 0). (3) once real-time output has been disabled (rtpoe0 bit = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1). chapter 13 real-time output function (rto) preliminary user?s manual u16895ej1v0ud 388 13.7 security function a circuit that sets the pin outputs to high impedance as a security functi on for when malfunctions of a stepping motor controlled by rto occur is provided on chip. it fo rcibly resets the pins allocated to rtp00 to rtp05 via external interrupt intp0 pin edge detection, placing them in t he high-impedance state. the ports (p50 to p55 pins) placed in high impedance by intp0 note 1 pin are initialized note 2 , so settings for these ports must be performed again. notes 1. regardless of the port settings, p50 to p55 pins are all placed in high impedance via the intp0 pin. 2. the bits that are initialized are a ll the bits corresponding to p50 to p 55 pins of the following registers. ? p5 register ? pm5 register ? pmc5 register ? pu5 register ? pfc5 register ? pf5 register the block diagram of the security function is shown below. figure 13-3. block diagra m of security function edge detection intc intp0 rtost0 rtpout00 to rtpout05 rtp00 to rtp05 ev dd r 6 this function is set with the pllctl.rtost0 bit. chapter 13 real-time output function (rto) preliminary user?s manual u16895ej1v0ud 389 (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the rto security function and pll. this register can be read or writt en in 8-bit or 1-bit units. after reset, pllctl is set to 01h. 0 pllctl 0 0 0 0 rtost0 selpll note pllon note intp0 pin is not used as trigger for security function intp0 pin is used as trigger for security function rtost0 0 1 control of rtp00 to rtp05 security function after reset: 01h r/w address: fffff806h < > < > < > note for details on the selpll and pllon bits, refer to chapter 6 clock generation function . cautions 1. before outputting a value to the real-time output po rts (rtp00 to rtp05), select the intp0 pin interrupt edge det ection and then set the rtost0 bit. 2. to set again the ports (p50 to p 55 pins) as real-time output ports after placing them in high impedance via th e intp0 pin, first cancel the security function. [procedure to set ports again] <1> cancel the security function and enable port setting by clearing the rtost0 bit to 0. <2> set the rtost0 bit to 1 (only if required). <3> set again as real-time output port. 3. be sure to clear bits 4 to 7 to 0. changing bit 3 does not affect the operation. preliminary user?s manual u16895ej1v0ud 390 chapter 14 a/d converter 14.1 overview the a/d converter converts analog input signals into digital values and has an 8-channel (ani0 to ani7) configuration. the a/d converter has the following functions. operating voltage (av ref0 ): 2.7 to 5.5 v successive approximation method 10-bit a/d converter analog input pin: 8 trigger mode: ? software trigger mode ? timer trigger mode (inttm010) ? external trigger mode (adtrg pin) operation mode ? select mode ? scan mode a/d conversion time: ? normal mode: 14 to 100 s @ 4.0 v av ref0 5.5 v 17 to 100 s @ 2.7 v av ref0 < 4.0 v ? high-speed mode: 3 to 100 s @ 4.5 v av ref0 5.5 v 4.8 to 100 s @ 4.0 v av ref0 < 4.5 v 6 to 100 s @ 2.85 v av ref0 < 4.0 v 14 to 100 s @ 2.7 v av ref0 < 2.85 v power fail detection function 14.2 functions (1) 10-bit resolution a/d conversion 1 analog input channel is selected from the ani0 to ani7 pins, and an a/d conversion operation with resolution of 10 bits is repeatedly executed. every ti me a/d conversion is completed, an interrupt request signal (intad) is generated. (2) power fail detection function this is a function to detect low voltage in a battery. the results of a/d conversi on (the value in the adcrh register) and the pft register are compared, and in tad signal is generated only when the comparison conditions match. chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 391 14.3 configuration the a/d converter consists of the following hardware. figure 14-1. block diag ram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 av ref0 av ss intad adcs bit 3 ads2 ads1 ads0 ega1 ega0 trg adtmd fr0 adhs1 adhs0 adcs2 adcs admd fr2 fr1 sample & hold circuit av ss voltage comparator controller edge detector adtrg inttm010 adcr/adcrh register pft register ads register adm register pfen pfcm pfm register internal bus sar register comparator tap selector selector selector table 14-1. registers of a/ d converter used by software item configuration registers a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read power fail comparison threshold register (pft) a/d converter mode register (adm) analog input channel specification register (ads) power fail comparison mode register (pfm) chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 392 (1) ani0 to ani7 pins these are analog input pins for the 8 channels of the a/ d converter. they are used to input analog signals to be converted into digital signals. pins other than thos e selected as analog input by the ads register can be used as input ports. (2) sample & hold circuit the sample & hold circuit samples the analog input si gnals selected by the input circuit and sends the sampled data to the voltage comparator. this ci rcuit holds the sampled analog input voltage during a/d conversion. (3) series resistor string the series resistor string is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (4) voltage comparator the voltage comparator com pares the value that is sampled and hel d with the output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage value with the voltage value from the series resistor string, and converts the comparison result starti ng from the most significant bit (msb). when the least significant bit (lsb) has been converted to a digital value (end of a/d conversion), the contents of the sar register are transfe rred to the adcr register. the sar register cannot be read or written directly. (6) a/d conversion result register (adcr) , a/d conversion result register h (adcrh) each time a/d conversion ends, the conversion results are loaded from the successive approximation register and the results of a/d conversion are held in the higher 10 bits of this regist er (the lower 6 bits are fixed to 0). (7) controller the controller compares the a/d c onversion results (the value of the adcrh register) with the value of the pft register when a/d conversion ends or the power fail detection function is used. it generates intad signal only when the comparison conditions match. (8) av ref0 pin this is the analog power supply pin/reference voltage input pin of the a/d converter. always use the same potential as the v dd pin even when not using the a/d converter. the signals input to the ani0 to ani7 pins are conv erted into digital signals based on the voltage applied across av ref0 and av ss . (9) av ss pin this is the ground potential pin of the a/d converter. always use the same potential as the v ss pin even when not using the a/d converter. chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 393 (10) a/d converter mode register (adm) this register sets the conversion time of the analog input to be converted to a digital signal and the conversion operation start/stop. (11) analog input channel sp ecification register (ads) this register specifies the input port for the analog voltage to be converted to a digital signal. (12) power fail comparis on mode register (pfm) this register sets the power fail detection mode. (13) power fail comparison threshold register (pft) this register sets the threshold to be compared with the adcr register. 14.4 registers the a/d converter is controlle d by the following registers. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? power fail comparison mode register (pfm) ? power fail comparison threshold register (pft) ? a/d conversion result register, a/d c onversion result register h (adcr, adcrh) chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 394 (1) a/d converter mode register (adm) this register sets the conversion time of the analog input signal to be convert ed into a digital signal as well as conversion start and stop. the adm register can be read or wr itten in 8-bit or 1-bit units. after reset, adm is cleared to 00h. adcs adcs 0 1 conversion operation stopped conversion operation enabled control of a/d conversion operation adm admd fr2 note 1 fr1 note 1 fr0 note 1 adhs1 note 1 adhs0 note 1 adcs2 admd 0 1 select mode scan mode control of operation mode adhs1 0 1 normal mode high-speed mode (valid only when av ref0 4.5 v) selection of 5 v a/d conversion time mode (av ref0 4.5 v) adhs0 0 1 normal mode high-speed mode (valid only when av ref0 2.7 or 2.85 v) selection of 3 v a/d conversion time mode (av ref0 2.7 or 2.85 v) after reset: 00h r/w address: fffff200h adcs2 0 1 reference voltage generator operation stopped reference voltage generator operation enabled control of reference voltage generator for boosting note 2 < > < > notes 1. for details of the fr2 to fr0 bits and the a/d conversion, refer to table 14-2 a/d conversion time . 2. the operation of the reference voltage generator fo r boosting is controlled by the adcs2 bit and it takes 1 or 14 s after operation is started until it is stabilized. therefore, if the adcs bit is set to 1 (a/d conversion is started) at least 1 or 14 s after the adcs2 bit was se t to 1 (reference voltage generator for boosting is on), the first conversion result is valid. cautions 1. changing bits fr2 to fr0, adhs1, a nd adhs0 while the adcs bit = 1 is prohibited (write access to the adm register is enabled and re writing of bits fr2 to fr0, adhs1, and adhs0 is prohibited). 2. setting adhs1 and adhs0 bits to 11 is prohibited. 3. when the main clock is stopped and the cpu is operating on the subclock, do not access the adm register using an access method that causes a wait. for details, refer to 3.4.8 (2). remark f xx : main clock frequency chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 395 table 14-2. a/d conversion time a/d conversion time ( s) adhs1 adhs0 fr2 fr1 fr0 20 mhz@ av ref0 4.5 v 16 mhz@ av ref0 4.0 v 8 mhz@ av ref0 2.85 v 8 mhz@ av ref0 2.7 v conversion time mode 0 0 0 0 0 288/f xx 14.4 18.0 36.0 36.0 0 0 0 0 1 240/f xx setting prohibited 15.0 30.0 30.0 0 0 0 1 0 192/f xx setting prohibited setting prohibited 24.0 24.0 normal mode av ref0 2.7 v 0 0 0 1 1 setting prohibited 0 0 1 0 0 144/f xx setting prohibited setting prohibited 18.0 18.0 0 0 1 0 1 120/f xx setting prohibited setting prohibited setting prohibited setting prohibited 0 0 1 1 0 96/f xx setting prohibited setting prohibited setting prohibited setting prohibited normal mode av ref0 2.7 v 0 0 1 1 1 setting prohibited 0 1 0 0 0 96/f xx 4.8 6.0 12.0 setting prohibited 0 1 0 0 1 72/f xx setting prohibited setting prohibited 9.0 setting prohibited 0 1 0 1 0 48/f xx setting prohibited setting prohibited 6.0 setting prohibited 0 1 0 1 1 24/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 2.85 v 0 1 1 0 0 224/f xx 11.2 14.0 28.0 28.0 0 1 1 0 1 168/f xx setting prohibited 10.5 21.0 21.0 0 1 1 1 0 112/f xx setting prohibited setting prohibited setting prohibited setting prohibited 0 1 1 1 1 56/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 2.7 v 1 0 0 0 0 72/f xx 3.6 setting prohibited setting prohibited setting prohibited 1 0 0 0 1 54/f xx setting prohibited setting prohibited setting prohibited setting prohibited 1 0 0 1 0 36/f xx setting prohibited setting prohibited setting prohibited setting prohibited 1 0 0 1 1 18/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 4.5 v 1 0 1 setting prohibited 1 1 setting prohibited chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 396 (a) controlling reference vo ltage generator for boosting when the adcs2 bit = 0, power to the a/d converter drops. the converter requires a setup time of 14 s (normal mode: adhs1 and adhs0 bits = 00) or 1 s (high-speed mode: adhs1 and adhs0 bits = 11) or more after the adcs2 bit has been set to 1. therefore, the result of a/ d conversion becomes valid from the first result by setting the adcs bit to 1 at least 14 or 1 s after the adcs2 bit has been set to 1. table 14-3. setting of adcs bit and adcs2 bit adcs adcs2 a/d co nversion operation 0 0 stopped status (dc power consumption path does not exist) 0 1 conversion standby mode (only the refer ence voltage generator for boosting consumes power) 1 0 conversion mode (reference voltage generator stops operation note 1 ) 1 1 conversion mode (reference voltage generator is operating note 2 ) notes 1. if the adcs and adcs2 bits are changed from 00b to 10b, the reference voltage generator for boosting automatically turns on. if the adcs bit is cleared to 0 while the adcs2 bit is 0, the voltage generator automatically turns off. in the software trigger mode (ads.trg bit = 0), use of the first a/d conversion result is prohibited. in the hardware trigger mode (trg bit = 1), use t he a/d conversion result on ly if a/d conversion is started after the lapse of the o scillation stabilization time of t he reference voltage generator for boosting. 2. if the adcs and adcs2 bits are changed from 00b to 11b, the reference voltage generator for boosting automatically turns on. if the adcs bit is cleared to 0 while the adcs2 bit is 1, the voltage generator stays on. in the software trigger mode (trg bit = 0), use of the first a/d conversion result is prohibited. in the hardware trigger mode (trg bit = 1), use t he a/d conversion result on ly if a/d conversion is started after the lapse of the o scillation stabilization time of t he reference voltage generator for boosting. figure 14-2. operation sequence comparator control conversion operation conversion standby conversion operation conversion stop adcs adcs2 note reference voltage generator for boosting: operating note 1 or 14 s or more are required for the operation of the reference voltage generator for boosting between when the adcs2 bit is set (1) and when the adcs bit is set (1). chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 397 (2) analog input channel specification register (ads) this register specifies the analog vo ltage input port for a/d conversion. the ads register can be read or wr itten in 8-bit or 1-bit units. after reset, ads is cleared to 00h. ega1 note 1 ads ega0 note 1 trg adtmd note 2 0 ads2 ads1 ads0 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani0 ani0, ani1 ani0 to ani2 ani0 to ani3 ani0 to ani4 ani0 to ani5 ani0 to ani6 ani0 to ani7 ads2 0 0 0 0 1 1 1 1 ads1 0 0 1 1 0 0 1 1 ads0 0 1 0 1 0 1 0 1 specification of analog input channel select mode scan mode no edge detection falling edge rising edge both rising and falling edges ega1 note 1 0 0 1 1 ega0 note 1 0 1 0 1 specification of external trigger signal (adtrg) edge after reset: 00h r/w address: fffff201h trg 0 1 software trigger mode hardware trigger mode trigger mode selection adtmd note 2 0 1 external trigger (adtrg pin input) timer trigger (inttm010 signal generated) specification of hardware trigger mode notes 1. the ega1 and ega0 bits are valid only when t he hardware trigger mode (trg bit = 1) and external trigger mode (adtrg pin input: adtmd bit = 1) are selected. 2. the adtmd bit is valid only when the hardware trigger mode (trg bit = 1) is selected. cautions 1. when the main clock is stopped and the cpu is operating on the subclock, do not access the ads register using an access method that cau ses a wait. for details, refer to 3.4.8 (2). 2. be sure to clear bit 3 to 0. chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 398 (3) a/d conversion result register, a/d conversion result register h (adcr, adcrh) the adcr and adcrh registers stor e the a/d conversion results. these registers are read-only in 16-bit or 8-bit units. however, specify the adcr register for 16-bit access, and the adcrh register for 8-bit access. in the adcr r egister, the 10 bits of conversion results are read in the higher 10 bits and 0 is read in the lower 6 bits. in the adcrh register, the higher 8 bits of the conversion results are read. after reset, these registers are undefined. after reset: undefined r address: fffff204h adcr ad9 ad8 ad7 ad6 ad0 0 0 0 0 0 0 ad1 ad2 ad3 ad4 ad5 ad9 adcrh ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: fffff205h caution when the main clock is st opped and the cpu is operating on the subclock, do not access the adcr and adcrh registers using an access method that causes a wait. fo r details, refer to 3.4.8 (2). chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 399 the following shows the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and a/d conversion results (adcr register). sar = int ( 1024 + 0.5) adcr note = sar 64 or, (sar ? 0.5) v in < (sar + 0.5) int ( ): function that returns the in teger part of the value in parentheses v in : analog input voltage av ref0 : voltage of av ref0 pin adcr: value in the adcr register note the lower 6 bits of the a dcr register are fixed to 0. the following shows the relationship between the ana log input voltage and a/ d conversion results. figure 14-3. relationship between analog input voltage and a/d conversion results 1023 1022 1021 ffc0h ff80h ff40h 3 2 1 0 00c0h 0080h 0040h 0000h input voltage/av ref0 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 a/d conversion results sar adcr v in av ref0 av ref0 1024 av ref0 1024 chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 400 (4) power fail comparison mode register (pfm) this register sets the power fail detection mode. the pfm register compares the value in the p ft register with the val ue of the adcrh register. the pfm register can be read or wr itten in 8-bit or 1-bit units. after reset, pfm is cleared to 00h. pfen pfen 0 1 power fail comparison disabled power fail comparison enabled selection of power fail comparison enable/disable pfm pfcm 0 0 0 0 0 0 pfcm 0 1 interrupt request signal (intad) generated when adcr pft interrupt request signal (intad) generated when adcr < pft selection of power fail comparison mode after reset: 00h r/w address: fffff202h < > < > caution when the main clock is stopped and the cpu is operating on the subclock, do not access the pfm register using an access method that causes a wait. for details, refer to 3.4.8 (2). (5) power fail comparison th reshold register (pft) the pft register sets the comparison value in the power fail detection mode. the 8-bit data set in the pft register is co mpared with the value of the adcrh register. the pft register can be read or written in 8-bit units. after reset, pft is cleared to 00h. pft after reset: 00h r/w address: fffff203h 76 54 321 0 caution when the main clock is stopped and the cpu is operating on the subclock, do not access the pft register using an access method that causes a wait. for details, refer to 3.4.8 (2). chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 401 14.5 operation 14.5.1 basic operation <1> select the channel whose analog signal is to be c onverted into a digital signal using the ads register. set the adm.adhs1 or adm.adhs0 bit. <2> set the adm.adcs2 bit to 1 and wait 1 or 14 s or longer. <3> set the adm.adcs bit to 1 to start a/d conversion. (steps <4> to <10> are executed by hardware.) <4> the sample & hold circuit samples the voltage input to the selected analog input channel. <5> after sampling for a specific time, the sample & hold circuit enters the hold stat us and holds the input analog voltage until it has been converted into a digital signal. <6> set bit 9 of the successive approximation register (sar) to 1. the tap selector sets the voltage tap of the series resistor string to (1/2) av ref0 . <7> the voltage comparator compares t he voltage difference between the voltage tap of the series resistor string and the analog input voltage. if the ana log input voltage is greater than (1/2) av ref0 , the msb of the sar register remains set to 1. if the analog input voltage is less than (1/2) av ref0 , the msb is cleared to 0. <8> next, bit 8 of the sar register is automatically se t to 1 and the next comparison starts. depending on the previously determined value of bit 9, the voltage tap of the series resistor string is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 the analog input voltage is compared with one of th ese voltage taps and bit 8 of the sar register is manipulated as follows depending on the result of the comparison. analog input voltage voltage tap: bit 8 = 1 analog input voltage voltage tap: bit 8 = 0 <9> the above steps are repeated until bit 0 of the sar register has been manipulated. <10> when comparison of all 10 bits of the sar register ha s been completed, the valid digital value remains in the sar register, and the value of the sar register is transferred and latched to the adcr register. at the same time, an a/d conversion end interrupt request signal (intad) is generated. <11> repeat steps <4> to <10> until the adcs bit is cleared to 0. for another a/d conversion, start at <3>. however, when operating the a/d converter with the adcs2 bit cleared to 0, start at <2>. chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 402 14.5.2 trigger modes the v850es/kf1+ has the following three trigger modes that set the a/d conv ersion start timing. these trigger modes are set by the ads register. ? ? ? chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 403 14.5.3 operation modes the following two operation modes are available. t hese operation modes are set by the adm register. ? select mode ? scan mode (1) select mode one input analog signal specified by the ads register while the adm.ad md bit = 0 is converted. when conversion is complete, the result of c onversion is stored in the adcr register. at the same time, the a/d conversion end interrupt r equest signal (intad) is generat ed. however, the intad signal may or may not be generated depending on setting of the pfm and pft registers. for details, refer to 14.5.4 power fail detection function . if anything is written to the adm, ads, pfm, and pft r egisters during conversion, a/ d conversion is aborted. in the software trigger mode, a/d conv ersion is started from the beginni ng again. in the hardware trigger mode, the a/d converter waits for a trigger. if the trigger is detected during conversion in hardwar e trigger mode, a/d conver sion is aborted and started again from the beginning. figure 14-4. example of select mode operat ion timing (ads.ads2 to ads.ads0 bits = 0001b) ani1 a/d conversion data 1 (ani1) data 2 (ani1) data 1 data 2 data 1 (ani1) data 2 (ani1) adcr intad conversion start set adcs bit = 1 conversion start set adcs bit = 1 conversion end conversion end chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 404 (2) scan mode in this mode, the analog signals specified by the ad s register and input from the ani0 pin while the adm.admd bit = 1 are sequentially selected and converted. when conversion of one analog input signal is complete, t he conversion result is st ored in the adcr register and, at the same time, the a/d conversion end interrupt request signal (intad) is generated. the a/d conversion results of all t he analog input signals are stored in t he adcr register. it is therefore recommended to save the contents of the adcr regist er to ram once a/d conversion of one analog input signal has been completed. in the hardware trigger mode (ads.trg bit = 1), the a/ d converter waits for a trigger after it has completed a/d conversion of the analog signals specified by the ads register and input from the ani0 pin. if anything is written to the adm, ads, pfm, and pft r egisters during conversion, a/ d conversion is aborted. in the software trigger mode, a/d conv ersion is started from the beginni ng again. in the hardware trigger mode, the a/d converter waits for a trigger. conversion starts again from the ani0 pin. if the trigger is detected during conversion in hardwar e trigger mode, a/d conver sion is aborted and started again from the beginning (ani0 pin). chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 405 figure 14-5. example of scan mode operati on timing (ads.ads2 to ads.ads0 bits = 0011b) (a) timing example a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) adcr intad conversion start set adcs bit = 1 conversion end ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter adcr register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 406 14.5.4 power fail detection function the conversion end interrupt request si gnal (intad) can be controlled as fo llows using the pfm and pft registers. ? if the pfm.pfen bit = 0, the intad signal is generated each time conversion ends. ? if the pfen bit = 1 and the pfm.pfcm bi t = 0, the conversion result (adcrh register) and the value of the pft register are compared when conversion ends, and the intad signal is generated only if adcrh pft. ? if the pfen and pfcm bits = 1, the conversion result and the value of t he pft register are compared when conversion ends, and the intad signal is generated only if adcrh < pft. ? because, when the pfen bit = 1, the conversion result is overwritt en after the intad signal has been generated, unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the actual operation differs from the operation described above (refer to figure 14-6 ). figure 14-6. power fail detection function (pfcm bit = 0) conversion operation adcrh pft intad ani0 80h 80h 7fh 80h ani0 ani0 ani0 note note if reading is not performed during this interval, the conv ersion result changes to the next conversion result. chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 407 14.5.5 setting method the following describes how to set registers. (1) when using the a/d con verter for a/d conversion <1> set (1) the adm.adcs2 bit. <2> select the channel and conversion time by setting the ads.ads2 to ads.ads0 bits and the adm.adhs1, adm.adhs0, and adm.fr2 to adm.fr0 bits. <3> set (1) the adm.adcs bit. <4> transfer the a/d conversion data to the adcr register. <5> an interrupt request signal (intad) is generated. chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 408 14.6 cautions (1) power consumpti on in standby mode the operation of the a/d converter st ops in the standby mode. at this time, the power consumption can be reduced by stopping the conversion operation (the adm.adcs bit = 0). figure 14-7 shows an example of how to reduce the power consumpti on in the standby mode. figure 14-7. example of how to redu ce power consumption in standby mode adcs series resistor string av ref0 p-ch av ss (2) input range of ani0 to ani7 pins use the a/d converter with the ani0 to ani7 pin input voltages within the specified range. if a voltage of av ref0 or higher or av ss or lower (even if within the absolute maxi mum ratings) is input to these pins, the conversion value of the channel is undefined. also, this may affect the conversion value of other channels. (3) conflicting operations (a) conflict between writing to t he adcr register and reading from adcr register upon the end of conversion reading the adcr register takes precedence. after the register has been read, a new conversion result is written to the adcr register. (b) conflict between writing to the adcr register and writing to the adm register or writing to the ads register upon the end of conversion writing to the adm register or ads register takes precedence. the adcr regist er is not written, and neither is the conversion end interr upt request signal (intad) generated. chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 409 (4) measures against noise to keep a resolution of 10 bits, be aware of noise on the av ref0 and ani0 to ani7 pins. the higher the output impedance of the analog input source, the greater the effect of noise. therefore, it is recommended to connect external capacitors as shown in figure 14-8 to reduce noise. figure 14-8. handling of analog input pins av ref0 ani0 to ani7 av ss v ss if noise of av ref0 or higher or av ss or lower could be generated, clamp with a diode with a small v f (0.3 v or lower). reference voltage input c = 100 to 1000 pf (5) ani0/p70 to ani7/p77 pins the analog input pins (ani0 to ani7) function alternately as input port pins (p70 to p77). when performing a/d conversion by selecting any of th e ani0 to ani7 pins, do not execute an input instruction to port 7 during conversion. th is may decrease the conversion resolution. if digital pulses are applied to the pin adjacent to the pin subject to a/d conversi on, the value of the a/d conversion may differ from the expected value because of coupling noise. therefore, do not apply pulses to the pin adjacent to the pin subject to a/d conversion. (6) input impedance of av ref0 pin a series resistor string of tens of k ? chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 410 (7) interrupt request flag (adic.adif bit) even when the ads register is changed, the adif bit is not cleared (0). therefore, if the analog input pin is changed during a/d conversion, the adif bit may be set (1) because a/d conversion of the previous analog input pin ends immediately before the ads register is rewritten. in a such case, note that if the adif bit is r ead immediately after the ads register ha s been rewritten, the adif bit is set (1) even though a/d conversion of the analog in put pin after the change has not been completed. when stopping a/d conversion once and resuming it, clea r the adif bit (0) before resuming a/d conversion. figure 14-9. a/d conversion end in terrupt request occurrence timing anin anin anin anim anim anin anim anim a/d conversion adcr intad ads rewrite (anin conversion start) ads rewrite (anim conversion start) anim conversion is not complete even though adif is set. remark n = 0 to 7 m = 0 to 7 (8) conversion results immediat ely after a/d conversion start if the adm.adcs bit is set to 1 within 1 or 14 s after the adm.adcs2 bit has been set to 1, or if the adcs bit is set to 1 with the adcs2 bit cleared to 0, the conver ted value immediately after the a/d conversion operation has started may not satisfy the rating. take appropr iate measures such as polling the a/d conversion end interrupt request signal (intad) and discarding the first conversion result. (9) reading a/d conversion result register (adcr) when the adm or ads register has been written, the contents of the adcr register may become undefined. when the conversion operation is complete, read the co nversion results before writing to the adm or ads register. a correct conversion result may not be able to be read at a timing other than the above. when the cpu is operating on the subclock and main clock oscillation (f x ) is stopped, do not read the adcr register. for details, refer to 3.4.8 (2) . chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 411 (10) a/d converter sampling time a nd a/d conversion start delay time the a/d converter sampling time differs depending on the se t value of the adm register. a delay time exists until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 14-10 and table 14-4. figure 14-10. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time conversion time register write response time/trigger response time sampling time sampling timing intad adcs bit 1 or ads register rewrite sampling time chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 412 table 14-4. a/d converter conversion time register write response time note trigger response time note adhs1 adhs0 fr2 fr1 fr0 conversion time sampling time min. max. min. max. 0 0 0 0 0 288/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 0 0 0 1 240/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 0 0 1 0 192/f xx 132/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 0 1 0 0 144/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 0 1 0 1 120/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 0 1 1 0 96/f xx 48/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 0 0 0 96/f xx 48/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 0 0 1 72/f xx 36/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 1 0 1 0 48/f xx 24/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 1 0 1 1 24/f xx 12/f xx 8/f xx 9/f xx 4/f xx 5/f xx 0 1 1 0 0 224/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 1 0 1 168/f xx 132/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 1 1 1 0 112/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 1 1 1 1 56/f xx 44/f xx 8/f xx 9/f xx 4/f xx 5/f xx 1 0 0 0 0 72/f xx 24/f xx 11/f xx 12/f xx 7/f xx 8/f xx 1 0 0 0 1 54/f xx 18/f xx 10/f xx 11/f xx 6/f xx 7/f xx 1 0 0 1 0 36/f xx 12/f xx 9/f xx 10/f xx 5/f xx 6/f xx 1 0 0 1 1 18/f xx 6/f xx 8/f xx 9/f xx 4/f xx 5/f xx other than above setting prohibited ? ? ? ? ? note each response time is the time after the wait period. for the wait function, refer to 3.4.8 (2) access to special on-chip peripheral i/o register . remark f xx : main clock frequency chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 413 (11) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 14-11. internal equi valent circuit of anin pin anin c out c in r in av ref0 r in c out c in 4.5 v 3 k ? 8 pf 15 pf 2.7 v 60 k ? 8 pf 15 pf remarks 1. the above values are reference values. 2. n = 0 to 7 chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 414 14.7 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltag e that can be identified. that is , the percentage of the analog input voltage per bit of digital output is called 1 lsb (least si gnificant bit). the percent age of 1 lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always r epresented by the following formula regardless of the resolution. 1 %fsr = (max. value of analog in put voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av ref0 ? 0)/100 = av ref0 /100 1 lsb is as follows when the resolution is 10 bits. 1 lsb = 1/2 10 = 1/1024 = 0.098 %fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, linearity error and erro rs that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. figure 14-12. overall error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref0 0 chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 415 (3) quantization error when analog values are converted to digital values, a 1/2 lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2 lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the over all error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 14-13. quan tization error 0 ?? 0 1 ?? 1 digital output quantization error 1/2 lsb 1/2 lsb analog input 0 av ref0 (4) zero-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0??000 to 0??001. figure 14-14. zero-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref0 digital output (lower 3 bits) analog input (lsb) -1 100 chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 416 (5) full-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (full scale ? 3/2 lsb) when the digital output changes from 1??110 to 1??111. figure 14-15. full-scale error 100 011 010 000 0 av ref0 av ref0 ?1 av ref0 ?2 av ref0 ?3 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (6) differential linearity error while the ideal width of code output is 1 lsb, this indicates the difference between the actual measurement value and the ideal value. figure 14-16. differential linearity error 0 av ref0 digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1 lsb width chapter 14 a/d converter preliminary user?s manual u16895ej1v0ud 417 (7) integral linearity error this shows the degree to which the conversion characterist ics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measur ement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 14-17. integral linearity error 0 av ref0 digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when the analog input vo ltage was applied to the time when the digital output was obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 14-18. sampling time sampling time conversion time preliminary user?s manual u16895ej1v0ud 418 chapter 15 asynchronous serial interface (uart) in the v850es/kf1+, two channels of asynchronous seri al interface (uart) are provided. of these channels, uart0 supports lin-bus. 15.1 features ? maximum transfer speed: 312.5 kbps ? full-duplex communications on-chip rxbn register on-chip txbn register ? two-pin configuration note txdn: transmit data output pin rxdn: receive data input pin ? reception error detection functions ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt request signal (intsren): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt request signal (int srn): interrupt is generated when receive data is transferred from the receive shift register to the rxbn register after serial transfer is completed during a reception enabled state ? transmission completion interrupt request signal (intstn): interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the transmit shift register is completed ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? msb-first or lsb-first transfer of data selectable (uart0 only) ? transmit data output level inversion function (uart0 only) ? 13 to 20 bits selectable for sync break field transmission (uart0 only) ? 11 bits or more identifiable for sync break fi eld reception (sbf reception flag (uart0 only)) ? on-chip dedicated baud rate generator note the asck0 pin (external clock i nput) is available only for uart0. remark n = 0, 1 chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 419 15.2 configuration table 15-1. configuration of uartn item configuration registers receive buffer register n (rxbn) transmit buffer register n (txbn) receive shift register transmit shift register asynchronous serial interface mode register n (asimn) asynchronous serial interface status register n (asisn) asynchronous serial interface tran smit status register n (asifn) lin operation control register 0 (asicl0) other reception control parity check addition of transmissi on control parity remark n = 0, 1 figure 15-1 shows the configuration of uartn. (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register for specifying the operation of uartn. (2) asynchronous serial interfa ce status register n (asisn) the asisn register consists of a set of flags that indicate the erro r contents when a reception error occurs. the various reception error flags are set (1) when a reception error occurs and are cleared (0) when the asisn register is read. (3) asynchronous serial interface tran smit status register n (asifn) the asifn register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, which indicates the hol d status of the t xbn register data, and the transmit shift register data flag, which indicates whether transmission is in progress. (4) lin operation control register 0 (asicl0) the asicl0 register is an 8-bit regi ster that controls the output forma t for sbf transmission/reception and transmission. the asicl0 register can be used only with uart0. (5) reception control parity check the receive operation is controlled according to the c ontents set in the asimn register. a check for parity errors is also performed during a re ceive operation, and if an error is detected, a value corresponding to the error contents is set in the asisn register. (6) receive shift register this is a shift register that converts the serial data t hat was input to the rxdn pin to parallel data. one byte of data is received, and if a stop bi t is detected, the receive data is transferred to the rxbn register. this register cannot be directly manipulated. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 420 (7) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for holdi ng receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, re ceive data is transferred from the re ceive shift register to the rxbn register, synchronized with the end of t he shift-in processing of one frame. also, the reception completion interrupt request signal (intsrn) is generated by t he transfer of data to the rxbn register. (8) transmit shift register this is a shift register that converts the parallel data that was transferred from the txbn register to serial data. when one byte of data is transferred fr om the txbn register, the shift regi ster data is output from the txdn pin. the transmission completion interrupt request signal (int stn) is generated synchronized with the completion of transmission of one frame. this register cannot be directly manipulated. (9) transmit buffer register n (txbn) the txbn register is an 8-bit buffer for transmit data. a transmit operation is star ted by writing transmit data to the txbn register. (10) addition of transmission control parity a transmit operation is controlled by adding a start bit, par ity bit, or stop bit to the data that is written to the txbn register, according to the contents that were set in the asimn register. figure 15-1. block diagram of uartn parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer register n (rxbn) receive shift register reception control parity check transmit buffer register n (txbn) transmit shift register addition of transmission control parity baud rate generator n intsren intsrn intstn rxdn txdn remark for the configuration of baud rate generator n, refer to figure 15-16 . chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 421 15.3 registers (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register t hat controls the uartn transfer operation. this register can be read or written in 8-bit or 1-bit units. after reset, asimn is set to 01h. cautions 1. when using uartn, be sure to set th e external pins related to uartn functions to the control mode before setting the cksrn and brgcn registers, and then set the uarten bit to 1. then set the other bits. 2. set the uarten and rxen bits to 1 while a high level is input to the rxdn pin. if these bits are set to 1 while a low level is input to the rxdn pin, reception will be started. (1/2) <7> uarten asimn (n = 0, 1) <6> txen <5> rxen 4 psn1 3 psn0 2 cln 1 sln 0 isrmn after reset: 01h r/w address: asim0 fffffa00h, asim1 fffffa10h uarten control of operating clock 0 stop clock supply to uartn. 1 supply clock to uartn. ? if the uarten bit is cleared to 0, uartn is asynchronously reset note . ? if the uarten bit = 0, uartn is reset. to operate uartn, first set the uarten bit to 1. ? if the uarten bit is cleared from 1 to 0, all the register s of uartn are initialized. to set the uarten bit to 1 again, be sure to re-set the registers of uartn. the output of the txdn pin goes high when transmission is disabled, regardless of the setting of the uarten bit. txen transmission enable/disable 0 disable transmission 1 enable transmission ? set the txen bit to 1 after setting the uarten bit to 1 at startup. clear the uarten bit to 0 after clearing the txen bit to 0 to stop. ? to initialize the transmission unit, clear (0) the txen bi t, and after letting 2 clock cycles (base clock) elapse, set (1) the txen bit again. if the txen bit is not set again, initialization may not be successful. (for details about the base clock, refer to 15.6.1 (1) base clock .) note the asisn, asifn, and rxbn registers are reset. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 422 (2/2) rxen reception enable/disable 0 disable reception note 1 enable reception ? set the rxen bit to 1 after setting the uarten bit to 1 at startup. clear the uarten bit to 0 after clearing the rxen bit to 0 to stop. ? to initialize the reception unit status, clear (0) the r xen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the rxen bit again. if the rxen bit is not set agai n, initialization may not be successful. (for details about the base clock, refer to 15.6.1 (1) base clock .) psn1 psn0 transmit operation receive operation 0 0 don?t output parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity ? to overwrite the psn1 and psn0 bits, fi rst clear (0) the txen and rxen bits. ? if ?0 parity? is selected for reception, no parity judgment is performed. therefore, no error interrupt is generated because the asisn.pen bit is not set. cln specification of character length of 1 frame of transmit/receive data 0 7 bits 1 8 bits ? to overwrite the cln bit, first clear (0) the txen and rxen bits. sln specification of stop bit length of transmit data 0 1 bit 1 2 bits ? to overwrite the sln bit, first clear (0) the txen bit. ? since reception is always done with a stop bit length of 1, the sln bit setting does not affect receive operations. isrmn enable/disable of generation of reception completi on interrupt request signals when an error occurs 0 generate a reception error interrupt request signal (intsren) as an interrupt when an error occurs. in this case, no reception completion interr upt request signal (intsrn) is generated. 1 generate a reception completion interrupt request si gnal (intsrn) as an interrupt when an error occurs. in this case, no reception error interrupt request signal (intsren) is generated. ? to overwrite the isrmn bit, first clear (0) the rxen bit. note when reception is disabled, the receive shift r egister does not detect a start bit. no shift-in processing or transfer processing to the rxbn regist er is performed, and t he contents of the rxbn register are retained. when reception is enabled, the receive shift operat ion starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the rxbn register. a reception completion interrupt request signal (intsrn) is also generated in synchronizati on with the transfer to the rxbn register. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 423 (2) asynchronous serial interfa ce status register n (asisn) the asisn register, which consists of 3 error flag bits (pen, fen, and oven), indicates the error status when uartn reception is complete. the asisn register is cleared to 00h by a read operation. when a recept ion error occurs, the rxbn register should be read and the error flag should be cl eared after the asisn register is read. this register is read-only in 8-bit units. after reset, asisn is cleared to 00h. cautions 1. when the asimn.uarten bit or asimn. rxen bit is cleared to 0, or when the asisn register is read, the pen, fen, and oven bits are cleared (0). 2. operation using a bit manipula tion instruction is prohibited. 3. when the main clock is stopped and th e cpu is operating on the subclock, do not access the asisn register using an access method that causes a wait. for details, refer to 3.4.8 (2). 7 0 asisn (n = 0, 1) 6 0 5 0 4 0 3 0 2 pen 1 fen 0 oven after reset: 00h r address: asis0 fffffa03h, asis1 fffffa13h pen status flag indicating a parity error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read 1 when reception was completed, the receive data parity did not match the parity bit ? the operation of the pen bit differs according to the settings of the asimn.psn1 and asimn.psn0 bits. fen status flag indicating framing error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read 1 when reception was completed, no stop bit was detected ? for receive data stop bits, only the first bit is checked regardless of the stop bit length. oven status flag indicating an overrun error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read 1 when uartn completed the next receive operation before reading receive data of the rxbn register ? when an overrun error occurs, the next receive data value is not written to the rxbn register and the data is discarded. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 424 (3) asynchronous serial interface tran smit status register n (asifn) the asifn register, which consists of 2 status flag bits, indicates the status during transmission. by writing the next data to the txbn register after data is transferred from the txbn register to the transmit shift register, transmit operations can be performed conti nuously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written afte r referencing the txbfn bit to prevent writing to the txbn register by mistake. this register is read-only in 8-bit or 1-bit units. after reset, asifn is cleared to 00h. 7 0 asifn (n = 0, 1) 6 0 5 0 4 0 3 0 2 0 <1> txbfn <0> txsfn after reset: 00h r address: asif0 fffffa05h, asif1 fffffa15h txbfn transmission buffer data flag 0 data to be transferred next to txbn register does not exist (when the asimn.uarten or asimn.txen bit is cleared to 0, or when data has been transf erred to the transmis sion shift register) 1 data to be transferred next exists in txbn register (d ata exists in txbn register when the txbn register has been written to) ? when transmission is performed continuousl y, data should be written to the txbn register after confirming that this flag is 0. if writing to txbn register is performed when this flag is 1, transmit data cannot be guaranteed. txsfn transmit shift register data flag (indi cates the transmission status of uartn) 0 initial status or a waiting transmi ssion (when the uarten or txen bit is cleared to 0, or when following transmission completion, the next data transfer fr om the txbn register is not performed) 1 transmission in progress (when data has been transferred from the txbn register) ? when the transmission unit is initializ ed, initialization should be executed a fter confirming that this flag is 0 following the occurrence of a transmission completion inte rrupt request signal (intstn). if initialization is performed when this flag is 1, transmit data cannot be guaranteed. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 425 (4) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for stor ing parallel data that had been converted by the receive shift register. when reception is enabled (asimn.rxen bit = 1), receive da ta is transferred from the receive shift register to the rxbn register, synchronized with the completion of th e shift-in processing of one frame. also, a reception completion interrupt request signal (intsrn) is gener ated by the transfer to the rxbn register. for information about the timing for generat ing this interrupt request, refer to 15.5.4 receive operation . if reception is disabled (asimn.rxen bit = 0), the contents of the rxbn register are retained, and no processing is performed for transferring data to the r xbn register even when the shift-in processing of one frame is completed. also, the intsrn signal is not generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error (asisn.oven bit = 1) occurs, the receive data at that time is not trans ferred to the rxbn register. the rxbn register becomes ffh when a reset is input or asimn.uarten bit = 0. this register is read-only in 8-bit units. 7 rxbn7 rxbn (n = 0, 1) 6 rxbn6 5 rxbn5 4 rxbn4 3 rxbn3 2 rxbn2 1 rxbn1 0 rxbn0 after reset: ffh r address: rxb0 fffffa02h, rxb1 fffffa12h (5) transmit buffer register n (txbn) the txbn register is an 8-bit buffe r register for setting transmit data. when transmission is enabled (asimn.txen bit = 1), the tr ansmit operation is started by writing data to txbn register. when transmission is disabled (txen bit = 0), even if data is written to the txbn regist er, the value is ignored. the txbn register data is transferr ed to the transmit shift register, and a transmission completion interrupt request signal (intstn) is generated, synchronized wit h the completion of the transmission of one frame from the transmit shift register. for information about t he timing for generating this interrupt request, refer to 15.5.2 transmit operation . when the asifn.txbfn bit = 1, writing must not be performed to the txbn register. this register can be read or written in 8-bit units. after reset, txbn is set to ffh. 7 txbn7 txbn (n = 0, 1) 6 txbn6 5 txbn5 4 txbn4 3 txbn3 2 txbn2 1 txbn1 0 txbn0 after reset: ffh r/w address: txb0 fffffa04h, txb1 fffffa14h chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 426 (6) lin operation control register 0 (asicl0) the asicl0 register is an 8-bit regi ster that controls the output forma t for sbf transmission/reception and transmission. this register can be read or written in 8-bit or 1-bit units. after reset, asicl0 is set to 16h. caution the asicl0 register is valid only for uart0. uart1 do es not support this register. sbrf0 note if asim0.uarte0 bit = 0 and asim0.rxe0 bit = 0 or if sbf reception has been completed correctly sbf reception in progress sbrf0 note 0 1 sbf reception status flag asicl0 sbrt0 sbtt0 sbl02 sbl01 sbl00 udir0 txdlv0 after reset: 16h r/w address: fffffa08h sbf is output with 13-bit length (default) sbf is output with 14-bit length sbf is output with 15-bit length sbf is output with 16-bit length sbf is output with 17-bit length sbf is output with 18-bit length sbf is output with 19-bit length sbf is output with 20-bit length sbl02 1 1 1 0 0 0 0 1 sbl01 0 1 1 0 0 1 1 0 sbl00 1 0 1 0 1 0 1 0 sbf transmission output width control reception trigger sbrt0 0 1 sbf reception trigger ? transmission trigger sbtt0 0 1 sbf transmission trigger ? msb lsb udir0 0 1 first-bit specification normal output of txd0 pin inverted output of txd0 pin txdlv0 0 1 enables/disables inverting txd0 pin output < > < > < > note the sbrf0 bit is read-only. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 427 (7) selector operation control register 0 (selcnt0) the selcnt0 register is an 8-bit register that selects the tm01 capture trigger. if selcnt0.isel00 is set to 1 (rxd0 pin is selected) when lin is used, the transfer rate for calculating the baud rate error can be checked using tm01. this register can be read or written in 8-bit or 1-bit units. after reset, selcnt0 is cleared to 00h. 0 selcnt0 0 0 0 0 0 0 isel00 after reset: 00h r/w address: fffff308h select ti010 (p35) pin select rxd0 (p31) pin isel00 0 1 selection of tm01 capture trigger (tm010) chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 428 15.4 interrupt request signals the following three types of interrupt re quest signals are generated from uartn. ? reception error interrupt request signal (intsren) ? reception completion interrupt request signal (intsrn) ? transmission completion interrupt request signal (intstn) the default priorities among these three types of interrupt request signals are, from high to low, reception error interrupt, reception completion interrup t, and transmission completion interrupt. table 15-2. generated interrupt re quest signals and default priorities interrupt request signal priority reception error interrupt request signal (intsren) 1 reception completion interrupt request signal (intsrn) 2 transmission completion interrupt request signal (intstn) 3 (1) reception error interrupt request signal (intsren) when reception is enabled, the intsren signal is generated according to the logical or of the three types of reception errors explained for the asisn register. whether the intsren signal or the intsrn signal is generated when an error occurs can be specified according to the isrmn bit. when reception is disabled, the intsren signal is not generated. (2) reception completion interr upt request signal (intsrn) when reception is enabled, the intsrn signal is generated when data is shifted in to the receive shift register and transferred to the rxbn register. the intsrn signal can be generated in place of the intsren signal according to the isrmn bit even when a reception error has occurred. when reception is disabled, the intsrn signal is not generated. (3) transmission completion inte rrupt request signal (intstn) the intstn signal is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 429 15.5 operation 15.5.1 data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consists of one data fr ame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 15-2. the character bit length within one data frame, the type of parity, and the stop bit length are specified according to the asimn register. also, data is transferred lsb first. figure 15-2. format of uartn transmit/receive data 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 430 15.5.2 transmit operation when the asimn.uarten bit is set to 1, a hi gh level is output from the txdn pin. then, when the asimn.txen bit is set to 1, transmission is enabled, and the transmit operat ion is started by writing transmit data to the txbn register. (1) transmission enabled state this state is set by the txen bit. ? txen bit = 1: transmission enabled state ? txen bit = 0: transmission disabled state since uartn does not have a cts (tr ansmission enabled signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (2) starting a transmit operation in the transmission enabled state, a trans mit operation is started by writing tr ansmit data to the txbn register. when a transmit operation is star ted, the data in the txbn register is tr ansferred to the transmit shift register. then, the transmit shift register out puts data to the txdn pin (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. (3) transmission interrupt when the transmit shift register bec omes empty, a transmission completion interrupt request signal (intstn) is generated. the timing for generating the intstn signa l differs according to the specification of the stop bit length. the intstn signal is generated at the same time that the last stop bit is output. if the data to be transmitted next has not been written to the txbn register, the transmit operation is suspended. caution normally, when the transmit shift register becomes empty, the intstn signal is generated. however, the intstn signal is not generated if the transmit shift register becomes empty due to reset. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 431 figure 15-3. uartn transmission completion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn (output) (a) stop bit length: 1 (b) stop bit length: 2 stop chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 432 15.5.3 continuous transmission operation uartn can write the next transmit data to the txbn register at the timing t hat the transmit shift register starts the shift operation. this enables an efficient transmission rate to be realized by continuously transmitting data even during the transmission completion interrupt service after th e transmission of one data frame. in addition, reading the asifn.txsfn bit after the occurrence of a transmission co mpletion interrupt request si gnal (intstn) enables the txbn register to be efficiently written twice (2 byte s) without waiting for the tr ansmission of 1 data frame. when continuous transmission is perform ed, data should be written after referenc ing the asifn register to confirm the transmission status and whether or not da ta can be written to the txbn register. caution the values of the asifn.txbfn and asifn.txsfn bits change 10 11 01 in continuous transmission. therefore, do not confirm the status based on the combination of the txbfn and txsfn bits. read only the txbfn bit during continuous transmission. txbfn whether or not writing to txbn register is enabled 0 writing is enabled 1 writing is not enabled caution when transmission is perfo rmed continuously, write the first tr ansmit data (first byte) to the txbn register and confirm that the txbfn bit is 0, and then write the next transmit data (second byte) to the txbn register. if writing to the txbn register is performed when the txbfn bit is 1, transmit data cannot be guaranteed. the communication status can be confir med by referring to the txsfn bit. txsfn transmission status 0 transmission is completed. 1 under transmission. cautions 1. when initializing the transmission unit wh en continuous transmissi on is completed, confirm that the txsfn bit is 0 afte r the occurrence of the transmission completion interrupt, and then execute initialization. if in itialization is performed when the txsfn bit is 1, transmit data cannot be guaranteed. 2. while transmission is being performed contin uously, an overrun error may occur if the next transmission is completed befo re the intstn interrupt servicing following the transmission of 1 data frame is executed. an overrun error can be detected by embedding a program that can count the number of transmit da ta and referencing the txsfn bit. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 433 figure 15-4. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write transmit data to txbn register write second byte transmit data to txbn register write transmit data to txbn register when reading asifn register, txbfn = 0? when reading asifn register, txsfn = 1? when reading asifn register, txsfn = 0? no no no no yes yes yes yes end of transmission processing chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 434 (1) starting procedure the procedure to start continuous transmission is shown below. figure 15-5. continuous tr ansmission starting procedure txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn, txsfn bits) 00 11 note 11 01 01 11 01 11 txsn register start bit stop bit stop bit start bit 10 note refer to 15.7 cautions (2) . asifn register transmission starting procedure internal operation txbfn txsfn ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit ? read asifn register (confirm that txbfn bit = 0) start data (1) transmission 1 0 0 0 1 note 1 1 1 ? write data (2) < chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 435 (2) ending procedure the procedure for ending continuous transmission is shown below. figure 15-6. continuous transmission end procedure txdn (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intstn (output) txbn register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asifn register (txbfn, txsfn bits) uarten bit or txen bit 11 01 11 01 00 txsn register start bit start bit stop bit stop bit asifn register transmission end procedure internal operation txbfn txsfn <6> transmission of data (m ? 2) is in progress 1 1 <7> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? 1) transmission < chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 436 15.5.4 receive operation the awaiting reception state is set by setting the asimn.uar ten bit to 1 and then setting the asimn.rxen bit to 1. to start the receive operatio n, start sampling at the fallin g edge when the falling of the rxdn pin is detected. if the rxdn pin is low level at a start bit sampling point, the st art bit is recognized. when the receive operation begins, serial data is stored sequentially in the receive shift regi ster according to the baud rate that was set. a reception completion interrupt request signal (intsrn) is generated each time the reception of one frame of data is completed. normally, the receive data is transferred from the rxbn register to memory by th is interrupt servicing. (1) reception enabled state the receive operation is set to the reception enabled state by setting the rxen bit to 1. ? rxen bit = 1: reception enabled state ? rxen bit = 0: reception disabled state in receive disabled state, the reception hardware stands by in the initial stat e. at this time, the contents of the rxbn register are retained, and no reception completion interrupt or reception error interrupt is generated. (2) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled using the serial clock from baud rate generator n (brgn). (3) reception completion interrupt when the rxen bit = 1 and the reception of one frame of data is completed (the stop bit is detected), the intsrn signal is generated and the receive data within t he receive shift register is transferred to the rxbn register at the same time. also, if an overrun error (asisn.oven bit = 1) occurs, t he receive data at that time is not transferred to the rxbn register, and either the intsrn signal or a re ception error interrupt request signal (intsren) is generated according to the asimn.isrmn bit setting. even if a parity error (asisn.pen bit = 1) or framing error (asisn.fen bit = 1) occurs during a reception operation, the receive operation contin ues until stop bit is received, and after reception is completed, either the intsrn signal or the intsren signal is generated according to the isrmn bit setting (the receive data within the receive shift register is transferred to the rxbn register). if the rxen bit is cleared (0) during a receive operation, the receive operation is immediately stopped. the contents of the rxbn register and the asisn register at this time do not change, and the intsrn signal or the intsren signal is not generated. the intsrn signal or the intsren signal is not gener ated when the rxen bit = 0 (reception is disabled). chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 437 figure 15-7. uartn reception completion inte rrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read th e rxbn register even when a recept ion error occurs. if the rxbn register is not read, an overrun error wil l occur at the next data reception and the reception error status will continue infinitely. 2. reception is always performed assuming a stop bit length of 1. a second stop bit is ignored. 15.5.5 reception error the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. as a result of data reception, the various flags of the asisn register ar e set (1), and a reception error interrupt request signal (intsren) or a reception completion interrupt request signal (intsrn) is generated at the same time. the asimn.isrmn bit specifies whether the intsren signal or the intsrn signal is generated. the type of error that occurred during reception can be de tected by reading the conten ts of the asisn register during the intsren or intsrn interrupt servicing. the contents of the asisn r egister are cleared (0) by reading the asisn register. table 15-3. reception error causes error flag reception error cause pen parity error the parity specificat ion during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from the rxbn register chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 438 (1) separation of reception e rror interrupt request signal a reception error interrupt request signal can be separ ated from the intsrn signal and generated as the intsren signal by clearing the isrmn bit to 0. figure 15-8. when reception error in terrupt request signal is separated from intsrn signal (isrmn bit = 0) (a) no error occurs during reception (b) an e rror occurs during reception intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn does not occur figure 15-9. when reception error in terrupt request signal is included in intsrn signal (isrmn bit = 1) (a) no error occurs during reception (b) an erro r occurs during reception intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsren does not occur chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 439 15.5.6 parity types and corresponding operation a parity bit is used to detect a bit error in communication da ta. normally, the same type of parity bit is used on the transmission and reception sides. (1) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the valu e ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the receive data includi ng the parity bit is counted, and a parity error is generated if this number is odd. (2) odd parity (i) during transmission in contrast to even parity, the parity bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the receive data includi ng the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (4) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no par ity bit. since there is no parity bit, no parity error is generated. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 440 15.5.7 receive data noise filter the rxdn signal is sampled at the risi ng edge of the prescaler output base clock (f uclk ). if the same sampling value is obtained twice, the ma tch detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to figure 15-11 ). refer to 15.6.1 (1) base clock regarding the base clock. also, since the circuit is configured as shown in figure 15-10, internal processing during a receive operation is delayed by up to 2 clocks accordin g to the external signal status. figure 15-10. noise filter circuit rxdn q base clock in ld_en q in internal signal a internal signal b match detector f uclk figure 15-11. timing of rx dn signal judg ed as noise internal signal a base clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 441 15.5.8 sbf transmission/ reception (uart0 only) the uart0 of the v850es/kf1+ has an sbf (sync break field) transmission/re ception control function to enable use of the lin function. remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to cont rol the switches, actuators, and s ensors, and these are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method a nd is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possibl e when the baud rate error in the slave is 15% or less. (1) sbf transmission/reception format figures 15-12 and 15-13 outline the transmission and reception manipulations of lin. figure 15-12. lin transmission manipulation outline sleep bus wakeup signal frame sync break field sync field ident field data field data field checksum field intst0 interrupt txd0 (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. sbf output is performed by hardwar e. the output width is the bi t length set by the asicl0.sbl02 to asicl0.sbl00 bits. if even finer output width adj ustments are required, such adjustments can be performed using the value of brg (refer to 15.6 dedicated baud rate generator n (brgn) ). 3. 80h transfer in the 8-bit mode is s ubstituted for the wakeup signal frame. 4. a transmission completion interrupt request si gnal (intst0) is output at the start of each transmission. the intst0 signal is also out put at the start of each sbf transmission. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 442 figure 15-13. lin reception manipulation outline reception interrupt (intuanr) edge detection capture timer disable disable enable txd0 (output) enable note 2 13 bits sbf reception note 3 note 4 note 1 sf reception id reception data transmission data transmission note 5 data transmission sleep bus wakeup signal frame sync break field sync field ident field data field data field checksum field notes 1. the wakeup signal is sent by the pin edge det ector, uart0 is enabled, and the sbf reception mode is set. 2. the receive operation is perform ed until detection of the stop bit. upon detection of sbf reception of 11 or more bits, normal sbf reception end is judged, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits , an sbf reception error is judged, no interrupt signal is output, and the mode return s to the sbf reception mode. 3. if sbf reception ends normally, an interrupt request signal is output. the timer is enabled by an sbf reception completion interrupt. moreover, e rror detection for the asi s0.pe0, asis0.fe0, and asis0.ove0 bits is suppressed and uart communi cation error detection processing and data transfer of the receive shift register and rxb0 register are not perform ed. the receive shift register holds the initial value, ffh. 4. the rxd0 pin is connected to ti (capture input: refer to 15.3 (7) selector operation control register 0 (selcnt0) ) of the timer, the transfer rate is calculated, and the baud rate error is calculated. the value of brg (refer to 15.6 dedicated baud rate generator n (brgn) ) obtained by correcting the baud rate error after dropping uart0 enable is set again, causing the status to become the reception status. 5. checksum field distinctions are made by software. uart0 is initialized following csf reception, and the processing for setting the sbf recepti on mode again is performed by software. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 443 (2) sbf transmission when the asim0.uarte0 bit = asim0.txe0 bit = 1, t he transmission enabled stat us is entered, and sbf transmission is started by setting the sbf trans mission trigger (asicl0.sbrt0 bit) to 1. thereafter, a low-level width of bits 13 to 20 specified by the asicl0.sb l02 to asicl0.sbl00 bits is output. a transmission completion interrupt request signal (i ntst0) is generated upon sbf transmission start. following the end of sbf transmission, the asicl0.sbtt0 bit is automatically cleared to 0. thereafter, the uart transmission mode is restored. transmission is suspended until the data to be transmitted next is written to the txb0 register, or until the sbf transmission trigger (sbtt0 bit) is set to 1. figure 15-14. sbf transmission intst0 interrupt 12345678910111213 stop bit setting of sbtt0 bit chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 444 (3) sbf reception the reception enabled status is ac hieved by setting the asim0.uarte0 bit to 1 and then setting the asim0.rxe0 bit to 1. the sbf reception wait status is set by setting the sbf reception trigger (asicl0.sbrt0 bit) to 1. in the sbf reception wait status, sim ilarly to the uart reception wait st atus, the rxd0 pin is monitored and start bit detection is performed. following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, normal processing is judged and a reception completion interrupt request signal (intsr0) is output. the asicl0. sbrf0 bit is automatically cleared and sbf reception ends. error detection for the asis0 .pe0, asis0.fe0, and asis0.ove0 bits is suppressed and uart communication error detection processing is not performed. moreover, data transfer of the reception shift register and rxb0 register is not perfo rmed and ffh, the initial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the sbf reception mode is returned to. the asicl0. sbrf0 bit is not clear ed at this time. figure 15-15. sbf reception (a) normal sbf reception (detection of stop bit in more than 10.5 bits) sbrf0 123456 11.5 7891011 intst0 interrupt (b) sbf reception error (detection of stop bit in 10.5 or fewer bits) sbrf0 123456 10.5 78910 intst0 interrupt chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 445 15.6 dedicated baud rate generator n (brgn) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by uartn. the dedicated baud ra te generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. 15.6.1 baud rate generator n (brgn) configuration figure 15-16. configuration of baud rate generator n (brgn) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external input asck0 note 2 f uclk note 1 selector uarten 8-bit counter match detector baud rate brgcn: mdln7 to mdln0 1/2 uarten and txen bits (or rxen bit) cksrn: tpsn3 to tpsn0 f xx notes 1. set f uclk so as to satisfy the following conditions. ? v dd = regc = 4.0 to 5.5 v: f uclk 12 mhz ? v dd = 4.0 to 5.5 v, regc = capacity: f uclk 6 mhz ? v dd = regc = 2.7 to 4.0 v: f uclk 6 mhz 2. asck0 pin input can be used only by uart0. remark f xx : main clock frequency (1) base clock when the asimn.uarten bit = 1, the clock selected a ccording to the cksrn.tpsn3 to cksrn.tpsn0 bits is supplied to the transmission/reception uni t. this clock is called the base clock (f uclk ). when the uarten bit = 0, f uclk is fixed to low level. chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 446 15.6.2 serial clock generation a serial clock can be generated according to the settings of the cksrn and brgcn registers. the base clock to the 8-bit counter is select ed by the cksrn.tpsn3 to cksrn.tpsn0 bits. the 8-bit counter divisor value can be set by the brgcn.mdln7 to brgcn.mdln0 bits. (1) clock select register n (cksrn) the cksrn register is an 8-bit register for selecting the base clock using the tpsn3 to tpsn0 bits. the clock selected by the tpsn3 to t psn0 bits becomes the base clock (f uclk ) of the transmission/reception module. this register can be read or written in 8-bit units. after reset, cksrn is cleared to 00h. caution clear the asimn.uarten bit to 0 before rewriti ng the tpsn3 to tpsn0 bits. 7 0 cksrn (n = 0, 1) 6 0 5 0 4 0 3 tpsn3 2 tpsn2 1 tpsn1 0 tpsn0 after reset: 00h r/w address: cksr0 fffffa06h, cksr1 fffffa16h tpsn3 tpsn2 tpsn1 tpsn0 base clock (f uclk ) note 1 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1,024 1 0 1 1 external clock note 2 (asck0 pin) other than above setting prohibited notes 1. set f uclk so as to satisfy the following conditions. ? v dd = regc = 4.0 to 5.5 v: f uclk 12 mhz ? v dd = 4.0 to 5.5 v, regc = capacity: f uclk 6 mhz ? v dd = regc = 2.7 to 4.0 v: f uclk 6 mhz 2. asck0 pin input clock can be used only by uart0. setting of uart1 is prohibited. remark f xx : main clock frequency chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 447 (2) baud rate generator c ontrol register n (brgcn) the brgcn register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uartn. this register can be read or written in 8-bit units. after reset, brgcn is set to ffh. caution if the mdln7 to mdln0 bits are to be o verwritten, the asimn.txen and asimn.rxen bits should be cleared to 0 first. 7 mdln7 brgcn (n = 0, 1) 6 mdln6 5 mdln5 4 mdln4 3 mdln3 2 mdln2 1 mdln1 0 mdln0 after reset: ffh r/w address: brgc0 fffffa07h, brgc1 fffffa17h mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 set value (k) serial clock 0 0 0 0 0 ? setting prohibited 0 0 0 0 1 0 0 0 8 f uclk /8 0 0 0 0 1 0 0 1 9 f uclk /9 0 0 0 0 1 0 1 0 10 f uclk /10 1 1 1 1 1 0 1 0 250 f uclk /250 1 1 1 1 1 0 1 1 251 f uclk /251 1 1 1 1 1 1 0 0 252 f uclk /252 1 1 1 1 1 1 0 1 253 f uclk /253 1 1 1 1 1 1 1 0 254 f uclk /254 1 1 1 1 1 1 1 1 255 f uclk /255 remarks 1. f uclk : frequency [hz] of base clock selected by cksrn.tpsn3 to cksrn.tpsn0 bits 2. k: value set by mdln7 to mdln0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock fo r the 8-bit counter divided by 2. 4. : don?t care chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 448 (3) baud rate the baud rate is the value obtained by the following formula. baud rate [bps] = f uclk = frequency [hz] of base clock selected by cksrn.tpsn3 to cksrn.tpsn0 bits k = value set by brgcn.mdln7 to brgcn. mdln0 bits (k = 8, 9, 10, ..., 255) (4) baud rate error the baud rate error is obtained by the following formula. error (%) = ? 1 100 [%] cautions 1. make sure that the baud rate erro r during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error durin g reception is within the allowable baud rate range during reception, which is described in 15.6.4 allowable baud rate range during reception. example: base clock frequency = 10 mhz = 10,000,000 hz setting of brgcn.mdln7 to brgcn.mdln0 bits = 00100001b (k = 33) target baud rate = 153,600 bps baud rate = 10,000,000/(2 33) = 151,515 [bps] error = (151,515/153,600 ? 1) 100 = ? 1.357 [%] f uclk 2 k actual baud rate (baud rate with error) target baud rate (normal baud rate) chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 449 15.6.3 baud rate setting example table 15-4. baud rate generator setting data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) f uclk k err f uclk k err f uclk k err 300 f xx /512 41h (65) 0.16 f xx /1024 1ah (26) 0.16 f xx /256 41h (65) 0.16 600 f xx /256 41h (65) 0.16 f xx /1024 0dh (13) 0.16 f xx /128 41h (65) 0.16 1200 f xx /128 41h (65) 0.16 f xx /512 0dh (13) 0.16 f xx /64 41h (65) 0.16 2400 f xx /64 41h (65) 0.16 f xx /256 0dh (13) 0.16 f xx /32 41h (65) 0.16 4800 f xx /32 41h (65) 0.16 f xx /128 0dh (13) 0.16 f xx /16 41h (65) 0.16 9600 f xx /16 41h (65) 0.16 f xx /64 0dh (13) 0.16 f xx /8 41h (65) 0.16 10400 f xx /64 0fh (15) 0.16 f xx /64 0ch (12) 0.16 f xx /32 0fh (15) 0.16 19200 f xx /8 41h (65) 0.16 f xx /32 0dh (13) 0.16 f xx /4 41h (65) 0.16 24000 f xx /32 0dh (13) 0.16 f xx /2 a7h (167) ? 0.20 f xx /16 0dh (13) 0.16 31250 f xx /32 0ah (10) 0.00 f xx /32 08h (8) 0.00 f xx /16 0ah (10) 0 33600 f xx /2 95h (149) ? 0.13 f xx /2 77h (119) 0.04 f xx 95h (149) ? 0.13 38400 f xx /4 41h (65) 0.16 f xx /16 0dh (13) 0.16 f xx /2 41h (65) 0.16 48000 f xx /16 0dh (13) 0.16 f xx /2 53h (83) 0.40 f xx /8 0dh (13) 0.16 56000 f xx /2 59h (89) 0.32 f xx /2 47h (71) 0.60 f xx 59h (89) 0.32 62500 f xx /16 0ah (10) 0.00 f xx /16 08h (8) 0.00 f xx /8 0ah (10) 0.00 76800 f xx /2 41h (65) 0.16 f xx /8 0dh (13) 0.16 f xx 41h (65) 0.16 115200 f xx /2 2bh (43) 0.94 f xx /2 23h (35) ? 0.79 f xx 2bh (43) 0.94 153600 f xx /2 21h (33) ? 1.36 f xx /4 0dh (13) 0.16 f xx 21h (33) ? 1.36 312500 f xx /4 08h (8) 0 f xx /2 0dh (13) ? 1.54 f xx /2 08h (8) 0.00 caution the allowable fre quency of the base clock (f uclk ) is as follows. ? v dd = regc = 4.0 to 5.5 v: f uclk 12 mhz ? v dd = 4.0 to 5.5 v, regc = capacity: f uclk 6 mhz ? v dd = regc = 2.7 to 4.0 v: f uclk 6 mhz remark f xx : main clock frequency f uclk : base clock frequency k: set values of brgcn.mdln7 to brgcn.mdln0 bits err: baud rate error [%] n = 0, 1 chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 450 15.6.4 allowable baud ra te range during reception the degree to which a discrepancy from the transmission des tination?s baud rate is allowed during reception is shown below. caution the equations described belo w should be used to set the ba ud rate error during reception so that it always is within the allowable error range. figure 15-17. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 15-17, after the start bit is detect ed, the receive data latch timing is determined according to the counter that was set by the brgc n register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ?1 brate: uartn baud rate k: brgcn register set value fl: 1-bit data length when the latch timing margin is 2 base clocks, the minimum allowable transfer rate (flmin) is as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 min fl + = ? ? = chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 451 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 max fl 11 10 ? = + ? = 11 fl k 20 2 k 21 max fl ? = therefore, the transfer destination?s minimum receivable baud rate (brmin) is as follows. brmin = (flmax/11) ? 1 = brate the allowable baud rate error of uartn and the trans fer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 15-5. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ?3.61% 20 +4.26% ?4.31% 50 +4.56% ?4.58% 100 +4.66% ?4.67% 255 +4.72% ?4.73% remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgcn register set value 22k 21k + 2 20k 21k ? 2 chapter 15 asynchronous serial interface (uart) preliminary user?s manual u16895ej1v0ud 452 15.6.5 transfer rate duri ng continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. however, on the reception si de, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 15-18. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f uclk yields the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows (when the stop bit length = 1). transfer rate = 11 fl + (2/f uclk ) 15.7 cautions cautions to be observed when using uartn are shown below. (1) when the supply of clocks to uart n is stopped (for example, in idle or stop mode), operation stops with each register retaining the value it had immediately before t he supply of clocks was st opped. the txdn pin output also holds and outputs the value it had imm ediately before the supply of clocks was stopped. however, operation is not gua ranteed after the supply of clocks is rest arted. therefore, after the supply of clocks is restarted, the circuits should be initialized by clearing the asimn.uarten, asimn.rxen, and asimn.txen bits to 000. (2) uartn has a 2-stage buffer configurat ion consisting of the txbn regist er and the transmission shift register, and has status flags (asifn.txbfn and as ifn.txsfn bits) that indicate t he status of each buffer. if the txbfn and txsfn bits are read in contin uous transmission, the value changes 10 11 01. for the timing to write the next data to the txbn register, read only the txbfn bit durin g continuous transmission. preliminary user?s manual u16895ej1v0ud 453 chapter 16 clocked serial interface 0 (csi0) in the v850es/kf1+, two channels of clocked se rial interface 0 (csi0) are provided. 16.1 features ? maximum transfer speed: 5 mbps ? master mode/slave mode selectable ? transmission data length: 8 bits or 16 bits can be set ? msb/lsb-first selectable for transfer data ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire type so0n: serial transmit data output si0n: serial receive data input sck0n: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion inte rrupt request signal (intcsi0n) ? transmission/reception mode or reception-only mode selectable ? two transmission buffer registers (sotbfn/sotbfln, sotbn/sotbln) and two reception buffer registers (sirbn/sirbln, sirben/sirbeln) are provided on chip ? single transfer mode/continuous transfer mode selectable remark n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 454 16.2 configuration csi0n is controlled via the csim0n register. (1) clocked serial interface mode register 0n (csim0n) the csim0n register is an 8-bit register t hat specifies the operation of csi0n. (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register that co ntrols the csi0n serial transfer operation. (3) serial i/o shift register 0n (sio0n) the sio0n register is a 16-bit shift register th at converts parallel data into serial data. the sio0n register is used for bot h transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by accessing the buffer register. (4) serial i/o shift register 0nl (sio0nl) the sio0nl register is an 8-bit shift register that converts parallel data into serial data. the sio0nl register is used for both transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations are started up by accessing the buffer register. (5) clocked serial interface recei ve buffer register n (sirbn) the sirbn register is a 16-bit buffer r egister that stores receive data. (6) clocked serial interface recei ve buffer register nl (sirbnl) the sirbnl register is an 8-bit buffer r egister that stores receive data. (7) clocked serial interface read-only r eceive buffer register n (sirben) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. (8) clocked serial interface read-only r eceive buffer register nl (sirbenl) the sirbenl register is an 8-bit buffer register that stores receive data. the sirbenl register is the same as the sirbnl register. it is used to read the contents of the sirbnl register. (9) clocked serial interface transm it buffer register n (sotbn) the sotbn register is a 16-bit buffer r egister that stores transmit data. (10) clocked serial interface transm it buffer register nl (sotbnl) the sotbnl register is an 8-bit buffer register that stores transmit data. (11) clocked serial interface initial tr ansmit buffer register n (sotbfn) the sotbfn register is a 16-bit buffer register that st ores the initial transmit data in the continuous transfer mode. chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 455 (12) clocked serial interface initial tran smit buffer register nl (sotbfnl) the sotbfnl register is an 8-bit buffe r register that stores initial tran smit data in the continuous transfer mode. (13) selector the selector selects the serial clock to be used. (14) serial clock controller controls the serial clock supply to the shift register. also controls the clock out put to the sck0n pin when the internal clock is used. (15) serial clock counter counts the serial clock output or i nput during transmission/reception, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) interrupt controller controls the interrupt request timing. remark n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 456 figure 16-1. block diagram of clocked serial interface selector transmission control so selection so latch transmit buffer register (sotbn/sotbnl) receive buffer register (sirbn/sirbnl) shift register (sio0n/sio0nl) initial transmit buffer register (sotbfn/sotbfnl) interrupt controller clock start/stop control & clock phase control serial clock controller sck0n intcsi0n so0n si0n control signal transmission data control f xx /2 6 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 f xx /2 to5n sck0n remarks 1. n = 0, 1 2. f xx : main clock frequency chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 457 16.3 registers (1) clocked serial interface mode register 0n (csim0n) the csim0n register controls the csi0n operation. this register can be read or written in 8-bit or 1-bit units (however, csotn bit is read-only). after reset, csim0n is cleared to 00h. caution overwriting the trmdn, ccln, dirn, csi tn, and auton bits can be done only when the csotn bit = 0. if these bits are overwritten when the csotn bit = 1, the operation cannot be guaranteed. chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 458 <7> csi0en csim0n (n = 0, 1) <6> trmdn 5 ccln <4> dirn 3 csitn 2 auton 1 0 <0> csotn after reset: 00h r/w address: csim00 fffffd00h, csim01 fffffd10h csi0en csi0n operation enable/disable 0 disable csi0n operation. 1 enable csi0n operation. the internal csi0n circuit can be reset note asynchronously by clearing the csi0en bit to 0. for the sck0n and so0n pin output status when the csi0en bit = 0, refer to 16.5 output pins . trmdn specification of transmission/reception mode 0 receive-only mode 1 transmission/reception mode when the trmdn bit = 0, reception is performed and the so0n pi n outputs a low level. data reception is started by reading the sirbn register. when the trmdn bit = 1, transmissi on/reception is started by writing data to the sotbn register. ccln specification of data length 0 8 bits 1 16 bits dirn specification of transfer direction mode (msb/lsb) 0 first bit of transfer data is msb 1 first bit of transfer data is lsb csitn control of delay of interrupt request signal 0 no delay 1 delay mode (interrupt request signal is delay ed 1/2 cycle compared to the serial clock) the delay mode (csitn bit = 1) is valid only in the master mode (csicn.cks0n2 to csicn.cks0n0 bits are not 111b). in the slave mode (cks0n2 to cks0n0 bits are 111b), do not set the delay mode. auton specification of single trans fer mode or continuous transfer mode 0 single transfer mode 1 continuous transfer mode csotn communication status flag 0 communication stopped 1 communication in progress the csotn bit is cleared (0) by writing 0 to the csi0en bit. note the csotn bit and the sirbn, sirbnl, sirbe, sirbenl, sion , and sionl registers are reset. remark n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 459 (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register t hat controls the csi0n transfer operation. this register can be read or written in 8-bit or 1-bit units. after reset, csicn is cleared to 00h. caution the csicn register can be overwri tten only when the csim0n.csi0en bit = 0. 7 0 csicn (n = 0, 1) 6 0 5 0 4 ckpn 3 dapn 2 cks0n2 1 cks0n1 0 cks0n0 after reset: 00h r/w address: csic0 fffffd01h, csic1 fffffd11h ckpn dapn specification of timing of transmitting/receiving data to/from sck0n 0 0 (type 1) do7 do6 do5 do4 do3 do2 do1 do0 di7 so0n (output) sck0n (i/o) si0n (input) di6 di5 di4 di3 di2 di1 di0 0 1 (type 2) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 1 0 (type 3) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 1 1 (type 4) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) cks0n2 cks0n1 cks0n0 serial clock note mode 0 0 0 f xx /2 master mode 0 0 1 f xx /2 2 master mode 0 1 0 f xx /2 3 master mode 0 1 1 f xx /2 4 master mode 1 0 0 f xx /2 5 master mode 1 0 1 f xx /2 6 master mode 1 1 0 clock generated by to5n master mode 1 1 1 external clock (sck0n pin) slave mode note set the serial clock so as to satisfy the following conditions. ? v dd = regc = 4.0 to 5.5 v: serial clock 5 mhz ? v dd = 4.0 to 5.5 v, regc = capacity: serial clock 2.5 mhz ? v dd = regc = 2.7 to 4.0 v: serial clock 2.5 mhz remark f xx : main clock frequency chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 460 (3) clocked serial interface receive buffe r registers n, nl (sirbn, sirbnl) the sirbn register is a 16-bit buffer r egister that stores receive data. when the receive-only mode is set (csim0n.trmdn bit = 0), the reception operati on is started by reading data from the sirbn register. this register is read-only in 16-bit units. when the lowe r 8 bits are used as the sirbnl register, this register is read-only in 8-bit units. in addition to reset input, this register is also clear ed to 0000h by clearing (0) the csim0n.csi0en bit. cautions 1. read the sirbn regist er only when a 16-bit data length has been set (csim0n.ccln bit = 1). read the sirbnl register only when an 8-bi t data length has been set (ccln bit = 0). 2. when the single transfer mode has been set (csim0n.aut on bit = 0), perform a read operation only in the idle state (csim0n.csotn bit = 0). if the sirbn or sirbnl register is read during data transfer, th e data cannot be guaranteed. (a) sirbn register 14 sirbn 14 13 sirbn 13 12 sirbn 12 2 sirbn 2 3 sirbn 3 4 sirbn 4 5 sirbn 5 6 sirbn 6 7 sirbn 7 8 sirbn 8 9 sirbn 9 10 sirbn 10 11 sirbn 11 15 sirbn 15 1 sirbn 1 0 sirbn 0 sirbn (n = 0, 1) after reset: 0000h r address: sirb0 fffffd02h, sirb1 fffffd12h (b) sirbnl register 7 sirbn7 sirbnl (n = 0, 1) 6 sirbn6 5 sirbn5 4 sirbn4 3 sirbn3 2 sirbn2 1 sirbn1 0 sirbn0 after reset: 00h r address: sirb0l fffffd02h, sirb1l fffffd12h chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 461 (4) clocked serial interface read-only receive buffer registers n, nl (sirben, sirbenl) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. even if the sirben register is read, the next operation will not start. the sirben register is used to read the conten ts of the sirbn register when the serial reception is not continued. this register is read-only in 16-bit units. however, when the lower 8 bits are used as the sirbenl register, the register is read-only in 8-bit units. in addition to reset input, this register is also clear ed to 0000h by clearing (0) the csim0n.csi0en bit. cautions 1. the receive operation is not started even if data is read from the sirben and sirbenl registers. 2. the sirben register can be read only if a 16-bit data length has been set (csim0n.ccln bit = 1). the sirbenl register can be read only if an 8-bit data length has been set (ccln bit = 0). (a) sirben register 14 sirben 14 13 sirben 13 12 sirben 12 2 sirben 2 3 sirben 3 4 sirben 4 5 sirben 5 6 sirben 6 7 sirben 7 8 sirben 8 9 sirben 9 10 sirben 10 11 sirben 11 15 sirben 15 1 sirben 1 0 sirben 0 sirben (n = 0, 1) after reset: 0000h r address: sirbe0 fffffd06h, sirbe1 fffffd16h (b) sirbenl register 7 sirben7 sirbenl (n = 0, 1) 6 sirben6 5 sirben5 4 sirben4 3 sirben3 2 sirben2 1 sirben1 0 sirben0 after reset: 00h r address: sirbe0l fffffd06h, sirbe1l fffffd16h chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 462 (5) clocked serial interface transmit bu ffer registers n, nl (sotbn, sotbnl) the sotbn register is a 16-bit buffer r egister that stores transmit data. when the transmission/reception mode is set (csim0n.trmd n bit = 1), the transmission operation is started by writing data to the sotbn register. this register can be read or written in 16-bit units. however, when the lower 8 bi ts are used as the sotbnl register, the register can be read or written in 8-bit units. after reset, this register is cleared to 0000h. cautions 1. access the sotbn register only when a 16-bit data length has been set (csim0n.ccln bit = 1). access the sotbnl register only when an 8-bi t data length has been set (ccln bit = 0). 2. when the single transfer mode is set (csim0n.auton bit = 0) , perform access only in the idle state (csim0n.csotn bit = 0). if the sotbn and sotbnl registers are accessed during data transfer, the da ta cannot be guaranteed. (a) sotbn register 14 sotbn 14 13 sotbn 13 12 sotbn 12 2 sotbn 2 3 sotbn 3 4 sotbn 4 5 sotbn 5 6 sotbn 6 7 sotbn 7 8 sotbn 8 9 sotbn 9 10 sotbn 10 11 sotbn 11 15 sotbn 15 1 sotbn 1 0 sotbn 0 sotbn (n = 0, 1) after reset: 0000h r/w address: sotb0 fffffd04h, sotb1 fffffd14h (b) sotbnl register 7 sotbn7 sotbnl (n = 0, 1) 6 sotbn6 5 sotbn5 4 sotbn4 3 sotbn3 2 sotbn2 1 sotbn1 0 sotbn0 after reset: 00h r/w address: sotb0l fffffd04h, sotb1l fffffd14h chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 463 (6) clocked serial interface initial transmit buffer registers n, nl (sotbfn, sotbfnl) the sotbfn register is a 16-bit buffer register that st ores initial transmission data in the continuous transfer mode. the transmission operation is not started even if data is writt en to the sotbfn register. this register can be read or written in 16-bit units. however, when the lower 8 bits are used as the sotbfnl register, the register can be read or written in 8-bit units. after reset, this register is cleared to 0000h. caution access the sotbfn register and sotbfnl regi ster only when a 16-bit data length has been set (csim0n.ccln bit = 1), and only when an 8- bit data length has been set (ccln bit = 0), respectively, and only in the idle state (csim0n.csotn bit = 0). if the sotbfn and sotbfnl registers are accessed during data transfer, the data cannot be guaranteed. (a) sotbfn register 14 sotbfn 14 13 sotbfn 13 12 sotbfn 12 2 sotbfn 2 3 sotbfn 3 4 sotbfn 4 5 sotbfn 5 6 sotbfn 6 7 sotbfn 7 8 sotbfn 8 9 sotbfn 9 10 sotbfn 10 11 sotbfn 11 15 sotbfn 15 1 sotbfn 1 0 sotbfn 0 sotbfn (n = 0, 1) after reset: 0000h r/w address: sotbf0 fffffd08h, sotbf1 fffffd18h (b) sotbfnl register 7 sotbfn7 sotbfnl (n = 0, 1) 6 sotbfn6 5 sotbfn5 4 sotbfn4 3 sotbfn3 2 sotbfn2 1 sotbfn1 0 sotbfn0 after reset: 00h r/w address: sotbf0l fffffd08h, sotbf1l fffffd18h chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 464 (7) serial i/o shift registers n, nl (sio0n, sio0nl) the sio0n register is a 16-bit shift register th at converts parallel data into serial data. the transfer operation is not started even if the s io0n register is read. this register is read-only in 16-bit units. however, when the lower 8 bi ts are used as the sio0nl register, the register is read-only in 8-bit units. in addition to reset input, this register is also clear ed to 0000h by clearing (0) the csim0n.csi0en bit. caution read the sio0n register and sio0nl re gister only when a 16-bi t data length has been set (csim0n.ccln bit = 1), and only when an 8-bit data length has been set (ccln bit = 0), respectively, and only in the idle state (csim0n.csotn bit = 0). if the sio0n and sio0nl registers are read during data tran sfer, the data cannot be guaranteed. (a) sio0n register 14 sion14 13 sion13 12 sion12 2 sion2 3 sion3 4 sion4 5 sion5 6 sion6 7 sion7 8 sion8 9 sion9 10 sion10 11 sion11 15 sion15 1 sion1 0 sion0 sio0n (n = 0, 1) after reset: 0000h r address: sio00 fffffd0ah, sio01 fffffd1ah (b) sio0nl register 7 sion7 sio0nl (n = 0, 1) 6 sion6 5 sion5 4 sion4 3 sion3 2 sion2 1 sion1 0 sion0 after reset: 00h r address: sio00l fffffd0ah, sio01l fffffd1ah chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 465 receive-only mode ? reading starts reception ? storing up to the (n ? 2)th data (other than the last two) when reception is complete, read the received data from this register. repeat this operation until the (n ? 2)th data has been received. (supplement) do not read the (n ? 1)th data from this register. if read, a reception operation starts and continuous transfer cannot be completed. storing the (n ? 1)th received data note 2 read the (n ? 1)th received data from this register when the (n ? 1)th or nth (last) data has been received. storing the nth (last) received data note 2 when the nth (last) data has been received, read the nth (last) data. ? not used ? not used continuous transfer note 1 transmission/reception mode storing up to the (n ? 1)th received data (other than the last) note 2 when reception is complete, read the received data from this register. repeat this operation until the (n ? 1)th data has been received. ? not used storing the nth (last) received data note 2 when the nth (last) transmission/reception is complete, read the nth (last) data. ? starting transmission/reception when written ? storing the data to be transmitted second and subsequently when transmission/reception is complete, write the data to be transmitted next to this register to start the next transmission/reception. storing the data to be transmitted first note 2 before starting transmission/reception (writing to sotbn), write the data to be transmitted first. receive-only mode ? reading starts reception ? storing received data ? first, read dummy data and start transfer. ? to perform reception of the next data after reception is complete, read the received data from this register. storing the data received last note 2 if reception of the next data will not be performed after reception is complete, read the received data from this register. ? not used ? not used ? not used single transfer transmission/reception mode storing received data note 2 when transmission and reception are complete, read the received data from this register. ? not used. ? not used. ? starting transmission/reception when written ? storing the data to be transmitted ? first, write a dummy data (ffh) to start transmission/reception. ? when transmission/reception is complete, write the data to be transmitted next. ? not used function use method function use method function use method function use method function use method r/w read read read write write table 16-1. use of each buffer register register name sirbn (sirbnl) sirben (sirbenl) sio0n (sio0nl) sotbn (sotbnl) sotbfn (sotbfnl) notes 1. it is assumed that the number of data to be transmitted is n. 2. neither reading nor writing will start communication. remark in the 16-bit mode, the registers not enclose d in parentheses are used; in the 8-bit mode, the registers in parentheses are us ed. chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 466 16.4 operation 16.4.1 transmission/reception completion interrupt request signal (intcsi0n) the intcsi0n signal is set (1) upon comple tion of data transmission/reception. writing to the csim0n register clears (0) the intcsi0n signal. caution the delay mode (csim0n.csi tn bit = 1) is valid only in th e master mode (csicn.cks0n2 to csicn.cks0n0 bits are not 111b). the delay m ode cannot be set when the slave mode is set (cks0n2 to cks0n0 bits = 111b). chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 467 figure 16-2. timing chart of intcsi0n signal output in delay mode (a) transmit/receive type 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n signal csotn bit delay (b) transmit/receive type 4 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n signal csotn bit delay remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 468 16.4.2 single transfer mode (1) usage in the receive-only mode (csim0n.trmdn bit = 0), co mmunication is started by reading the sirbn/sirbnl register. in the transmission/reception mode (trmdn bit = 1) , communication is started by writing to the sotbn/sotbnl register. in the slave mode, the operation must be en abled beforehand (csim0n.csi0en bit = 1). when communication is started, t he value of the csim0n.csotn bit becomes 1 (transmission execution status). upon communication completion, the transmission/recepti on completion interrupt request signal (intcsi0n) is generated, and the csotn bit is cleared (0). t he next data communication request is then waited for. caution when the csotn bit = 1, do not manipulate the csi0n register. remark n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 469 figure 16-3. timing chart in single transfer mode (1/2) (a) in transmission/recepti on mode, data length: 8 bits , transfer direction: msb first, no interrupt delay, single transfer mode, when aah is received and 55h is transmitted, transmit/receive type 1 01010101 10101010 (55h) (aah) aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n signal 55h (transmit data) write 55h to sotbnl register remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. for the transmit/receive types, refer to 16.3 (2) clocked serial interface clock selection register n (csicn) . 3. n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 470 figure 16-3. timing chart in single transfer mode (2/2) (b) in transmission/reception mode, da ta length: 8 bits, transfer directi on: msb first, no interrupt delay, single transfer mode, when aah is received and 55h is transmitted, transmit/receive type 2 01010101 10101010 aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n signal (55h) (aah) 55h (transmit data) write 55h to sotbnl register remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. for the transmit/receive types, refer to 16.3 (2) clocked serial interface clock selection register n (csicn) . 3. n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 471 16.4.3 continuous transfer mode (1) usage (receive-only: 8-bit data length) <1> set the continuous transfer mode (csim0n. auton bit = 1) and the receive-only mode (csim0n.trmdn bit = 0). <2> read the sirbnl register (start transfer with dummy read). <3> when the transmission/reception completion interr upt request signal (intcs i0n) has been generated, read the sirbnl register note (reserve next transfer). <4> repeat step <3> (n ? 2) times. (n: number of transfer data) ignore the interrupt trigger ed by reception of the (n ? 1)th data (at this time, the sirbenl register can be read). <5> following generation of the last intcsi0n sign al, read the sirbenl r egister and the sio0nl register note . note when transferring n number of data, receive data is loaded by reading the sirbnl register from the first data to the (n ? 2)th data. the (n ? 1)th data is loaded by readi ng the sirbenl register, and the nth (last) data is loaded by readi ng the sio0nl register (refer to table 16-1 use of each buffer register ). chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 472 figure 16-4. continuous transf er (receive-only) timing chart ? transmit/receive type 1, 8-bit data length din-1 sck0n (i/o) si0n (input) so0n (output) l sio0nl register sirbnl register reg_rd csotn bit intcsi0n signal rq_clr trans_rq din-2 din-1 sirbn (dummy) sirbn (d1) sirbn (d2) sirbn (d3) sirben (d4) sio0n (d5) <3> <5> <3> <3> <4> period during which next transfer can be reserved <2> <1> din-2 din-3 din-4 din-5 din-5 din-3 din-4 remarks 1. reg_rd: internal signal. this signal indica tes that the sirbnl register has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. 2. n = 0, 1 in the case of the continuous transfer mode, two transfer requests are set at the star t of the first transfer. following the intcsi0n signal, transfer is continued if the sirbnl register can be read within the next transfer reservation period. if the sirbnl register cannot be read, transfer ends and the sirbnl register does not receive the new value of the sio0nl register. the last data can be obtained by reading the sio0nl register following completion of the transfer. chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 473 (2) usage (transmission/reception: 8-bit data length) <1> set the continuous transfer mode (csim0n.au ton bit = 1) and the transmission/reception mode (csim0n.trmdn bit = 1). <2> write the first data to the sotbfnl register. <3> write the 2nd data to the sotb nl register (start transfer). <4> when the transmission/reception completion interr upt request signal (intcs i0n) has been generated, write the next data to the sotbnl regi ster (reserve next transfer). re ad the sirbnl register to load the receive data. <5> repeat step <4> as long as data to be sent remains. <6> when the intcsi0n signal is generated, r ead the sirbnl register to load the (n ? 1)th receive data (n: number of transfer data). <7> following the last intcsi0n signal, read the sio0nl register to load the nth (last) receive data. chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 474 figure 16-5. continuous transfer (transmission/reception) timing chart ? transmit/receive type 1, 8-bit data length dout-1 dout-1 sck0n (i/o) so0n (output) si0n (input) sotbfnl register sotbnl register sio0nl register sirbnl register reg_wr reg_rd csotn bit intcsi0n signal rq_clr trans_rq dout-2 dout-3 dout-4 dout-5 dout-2 dout-3 dout-4 dout-5 din-1 din-1 sotbfn (d1) sotbn (d2) sotbn (d3) sotbn (d4) sotbn (d5) sirbn (d1) sirbn (d2) < 5 >< 7 >< 8 > < 4 > < 5 > < 4 > < 6 > period during which next transfer can be reserved < 5 > < 4 > < 3 > < 2 > < 1 > sirbn (d3) sirbn (d4) sio0n (d5) din-2 din-3 din-4 din-5 din-2 din-3 din-4 din-5 remarks 1. reg_wr: internal signal. this signal indicate s that the sotbnl regist er has been written. reg_rd: internal signal. this signal indica tes that the sirbnl register has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. 2. n = 0, 1 in the case of the continuous transfe r mode, two transfer requests are set at the start of the first transfer. following the intcsi0n signal, transfer is continued if the sotbnl register can be written within the next transfer reservation period. if the sotbnl register cannot be written, transfer ends and the sirbnl register does not receive the new value of the sio0nl register. the last receive data can be obtained by reading the sio0nl register follo wing completion of the transfer. chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 475 (3) next transfer reservation period in the continuous transfer mode, the next transfer mu st be prepared with the period shown in figure 16-6. figure 16-6. timing chart of next transfer reservation period (1/2) (a) when data length: 8 bits, transmit/receive type 1 sck0n (i/o) intcsi0n signal reservation period: 7 sck0n cycles (b) when data length: 16 bi ts, transmit/receive type 1 sck0n (i/o) intcsi0n signal reservation period: 15 sck0n cycles remark n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 476 figure 16-6. timing chart of next transfer reservation period (2/2) (c) when data length: 8 bi ts, transmit/receive type 2 sck0n (i/o) intcsi0n signal reservation period: 6.5 sck0n cycles (d) when data length: 16 bi ts, transmit/receive type 2 sck0n (i/o) intcsi0n signal reservation period: 14.5 sck0n cycles remark n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 477 (4) cautions to continue continuous transfers, it is necessary to either read the sirb n register or write to the sotbn register during the transfer reservation period. if access is performed to the sirbn register or the so tbn register when the transfer reservation period is over, the following occurs. (i) in case of conflict between transfer request clear and register access since transfer request clear has higher priority, the nex t transfer request is ignored. therefore, transfer is interrupted, and normal data transfer cannot be performed. figure 16-7. transfer request clear and register access conflict sck0n (i/o) intcsi0n signal rq_clr reg_r/w transfer reservation period remarks 1. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 478 (ii) in case of conflict between tr ansmission/reception completion inte rrupt request sign al (intcsi0n) generation and register access since continuous transfer has stopped once, ex ecuted as a new continuous transfer. in the slave mode, a bit phase erro r transfer error results (refer to figure 16-8 ). in the transmission/reception mode, the value of the so tbfn register is retransmitted, and illegal data is sent. figure 16-8. interrupt request and register ac cess conflict sck0n (i/o) intcsi0n signal rq_clr reg_r/w transfer reservation period 01 234 remarks 1. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1 chapter 16 clocked serial interface 0 (csi0) preliminary user?s manual u16895ej1v0ud 479 16.5 output pins the following describes the output pins. for the setting of each pin, refer to table 4-14 settings when port pins are used for alternate functions . (1) sck0n pin when the csi0n operation is disabled (csim0n.csi0en bi t = 0), the sck0n pin output status is as follows. table 16-2. sck0n pin output status ckpn cks0n2 cks0n1 cks0n0 sck0n pin output 0 don?t care don?t care don?t care fixed to high level 1 1 1 high impedance 1 other than above fixed to low level remark n = 0, 1 (2) so0n pin when the csi0n operation is disabled (csi0en bit = 0), the so0n pin output status is as follows. table 16-3. so0n pin output status trmdn dapn auton ccln dirn so0n pin output 0 don?t care don?t care don?t care don?t care fixed to low level 0 don?t care don?t care don?t care so latch value (low level) 0 sotbn7 bit value 0 1 sotbn0 bit value 0 sotbn15 bit value 0 1 1 sotbn0 bit value 0 sotbfn7 bit value 0 1 sotbfn0 bit value 0 sotbfn15 bit value 1 1 1 1 1 sotbfn0 bit value remark n = 0, 1 preliminary user?s manual u16895ej1v0ud 480 chapter 17 clocked serial interface a (csia) with automatic transmit /receive function in the v850es/kf1+, one channel of csia is provided. 17.1 functions csia0 has the following two modes. ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function (1) 3-wire serial i/o mode this mode is used to transfer 8-bit data using three lines : a serial clock pin (scka0) and two serial data pins (sia0 and soa0). in addition, whether 8-bit data is transferred msb or lsb first can be specified, so this interface can be connected to any device. (2) 3-wire serial i/o mode with auto matic transmit/receive function this mode is used to transfer 8-bit data using three lines : a serial clock pin (scka0) and two serial data pins (sia0 and soa0). in addition, whether 8-bit data is transferred msb or lsb first can be specified, so this interface can be connected to any device. data can be transferred to/from a display driver etc. without using software since a 32-byte buffer ram is incorporated for automatic transfer. ? maximum transfer speed: 2 mhz (in master mode) ? master mode/slave mode selectable ? transfer data length: 8 bits ? msb/lsb-first selectable for transfer data ? automatic transmit/receive function: number of transfer bytes c an be specified between 1 and 32 transfer interval can be specified (0 to 63 clocks) single transfer/repeat transfer selectable ? on-chip dedicated baud rate generator (6/8/16/32 divisions) ? 3-wire soa0: serial data output sia0: seri al data input scka0: serial clock i/o ? transmission/reception completion interrupt request signal: intcsia0 ? internal 32-byte buffer ram chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 481 17.2 configuration csia0 consists of the following hardware. table 17-1. configuration of csia0 item configuration registers serial i/o shi ft register a0 (sioa0) automatic data transfer address count register 0 (adtc0) csia0 buffer ram (csia0bm, csia0bml, csia0bmh) (m = 0 to f) control registers serial operation mode specification register 0 (csima0) serial status register 0 (csis0) serial trigger register 0 (csit0) divisor selection register 0 (brgca0) automatic data transfer address point specification register 0 (adtp0) automatic data transfer interval specification register 0 (adti0) remark for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions . chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 482 figure 17-1. block diagram of csia0 f xx /6 to f xx /256 master0 scka0 soa0 sia0 dira0 atm0 cksa01 cksa00 atstp0 atsta0 tsf0 intcsia0 rxea0 txea0 2 2 f xx buffer ram automatic data transfer address point specification register 0 (adtp0) automatic data transfer address count register 0 (adtc0) internal bus divisor selection register 0 (brgca0) serial i/o shift register a0 (sioa0) serial trigger register 0 (csit0) serial status register 0 (csis0) selector selector 6-bit counter interrupt generator serial transfer controller serial clock counter automatic data transfer interval specification register 0 (adti0) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 483 (1) serial i/o shift register a0 (sioa0) this is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (csima0.ate0 bit = 0). writing transmit data to the sioa0 regist er starts the transfer. in addition, after a transfer completion interrupt request signal (intcsia0) is generat ed (csis0.tsf0 bit = 0), data can be received by reading data from the sioa0 register. this register can be read or written in 8-bit units. ho wever, writing to the sioa0 register is prohibited when the tsf0 bit = 1. after reset, this register is cleared to 00h. cautions 1. a transfer operation is started by writing to the sioa 0 register. consequently, when transmission is disabled (csima0.txea0 bi t = 0), write dummy data to the sioa0 register to start the transfer operation, and then perform a receive operation. 2. do not write data to the sioa0 register while the automatic transm it/receive function is operating. 7 sioa07 sioa0 6 sioa06 5 sioa05 4 sioa04 3 sioa03 2 sioa02 1 sioa01 0 sioa00 after reset: 00h r/w address: fffffd46h (2) automatic data transfer a ddress count register 0 (adtc0) this is a register used to indicate buffer ram addresses during automatic transfer. when automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading adtc0 register value. this register is read-only in 8-bit units. however, reading from the adtc0 register is prohibited when the csis0.tsf0 bit = 1. after reset, this register is cleared to 00h. 7 adtc07 adtc0 6 adtc06 5 adtc05 4 adtc04 3 adtc03 2 adtc02 1 adtc01 0 adtc00 after reset: 00h r address: fffffd47h 17.3 registers serial interface csia0 is controlle d by the following six registers. ? serial operation mode specif ication register 0 (csima0) ? serial status register 0 (csis0) ? serial trigger register 0 (csit0) ? divisor selection register 0 (brgca0) ? automatic data transfer address point specification register 0 (adtp0) ? automatic data transfer interval specification register 0 (adti0) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 484 (1) serial operation mode speci fication register 0 (csima0) this is an 8-bit register used to c ontrol the serial transfer operation. this register can be read or written in 8-bit or 1-bit units. after reset, this register is cleared to 00h. <7> csiae0 disable csia0 operation (soa0: low level, scka0: high level) enable csia0 operation csiae0 0 1 csia0 operation enable/disable control csima0 6 ate0 5 atm0 4 master0 <3> txea0 <2> rxea0 <1> dira0 0 0 1-byte transfer mode automatic transfer mode ate0 0 1 automatic transfer operation enable/disable control single transfer mode (stops at address specified with adtp0 register) repeat transfer mode (following transfer completion, the adtc0 register is cleared to 00h and transmission starts again.) atm0 0 1 specification of automatic transfer mode slave mode (synchronized with scka0 input clock) master mode (synchronized with internal clock) master0 0 1 specification of csia0 master/slave mode disable transmission (soa0: low level) enable transmission txea0 0 1 transmission enable/disable control disable reception enable reception rxea0 0 1 reception enable/disable control msb first lsb first dira0 0 1 specification of transfer data direction after reset: 00h r/w address: fffffd40h when the csiae0 bit is cleared to 0, the csia0 unit is reset note asynchronously. when the csiae0 bit = 0, the csia0 unit is reset, so to operate csia0, first set the csiae0 bit to 1. if the csiae0 bit is cleared from 1 to 0, all the registers in the csia0 unit are initialized. before the csiae0 bit is set to 1 again, first re-set the registers of the csia0 unit. if the csiae0 bit is cleared from 1 to 0, the buffer ram value is not held. also, when the csiae0 bit = 0, the buffer ram cannot be accessed. note the adtc0, csit0, and sioa0 regi sters and the csis0.tsf0 bit are reset. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 485 (2) serial status register 0 (csis0) this is an 8-bit register used to select the serial clock and to indicate the transfer status of csia0. this register can be read or written in 8-bit or 1-bit units. after reset, this register is cleared to 00h. however, rewriting the csis0 register is prohibited when the tsf0 bit is 1. 7 cksa01 f xx f xx /2 f xx /4 f xx /8 20 mhz setting prohibited 100 ns 200 ns 400 ns 16 mhz setting prohibited 125 ns 250 ns 500 ns 10 mhz 100 ns 200 ns 400 ns 800 ns cksa01 0 0 1 1 cksa00 0 1 0 1 serial clock (f scka ) selection note csis0 6 cksa00 5 0 4 0 3 0 2 0 1 0 0 tsf0 csiae0 bit = 0 at reset input at completion of specified transfer when transfer has been suspended by setting the csit0.atstp0 bit to 1 from transfer start to completion of specified transfer rewriting csis0 is prohibited when the csima0.csiae0 bit is 1. tsf0 0 1 transfer status after reset: 00h r/w address: fffffd41h note set f scka so as to satisfy the following conditions. ? v dd = regc = 4.0 to 5.5 v: f scka 12 mhz ? v dd = 4.0 to 5.5 v, regc = capacity: f scka 6 mhz ? v dd = regc = 2.7 to 4.0 v: f scka 6 mhz cautions 1. the tsf0 bit is read-only. 2. when the tsf0 bit = 1, rewriting the csima0, csis0, brgca0, adtp0, adti0, and sioa0 regi sters is prohibited. however, the transfer buffe r ram can be rewritten. 3. be sure to clear bits 1 to 5 to 0. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 486 (3) serial trigger register 0 (csit0) the csit0 register between the buffer ram and shif t register is an 8-bit register used to control execution/stop of autom atic data transfer. this register can be read or written in 8-bit or 1-bi t units. however, manipulate only when the csima0.ate0 bit is 1 (manipulation prohibited when ate0 bit = 0). after reset, this register is cleared to 00h. 7 0 csit0 6 0 5 0 4 0 3 0 2 0 <1> atstp0 <0> atsta0 ? stop automatic data transfer atstp0 0 1 automatic data transfer suspension even when the atstp0 bit is set to 1, transfer does not stop until 1 byte has been transferred. 1 is held until immediately before the transmission/reception completion interrupt request signal (intcsia0) is generated, and atstp0 is automatically cleared to 0 after that. after automatic transfer has been suspended, the data address at the point of suspension is stored in the adtc0 register. a function to resume automatic data transfer is not provided, so if transfer has been interrupted by setting the atstp0 bit to 1, set each register again, and set the atsta0 bit to 1 to start automatic data transfer. after reset: 00h r/w address: fffffd42h ? start automatic data transfer atsta0 0 1 automatic data transfer start even when the atsta0 bit is set to 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the intcsia0 signal is generated, and atsta0 is automatically cleared to 0 after that. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 487 (4) divisor selection register 0 (brgca0) this is an 8-bit register used to control the se rial transfer speed (divisor of csia clock). this register can be read or written in 8-bit units. however, when the csis0.tsf0 bit is 1, rewriting the brgca0 register is prohibited. after reset, this register is set to 03h. 7 0 brgc01 0 0 1 1 brgc00 0 1 0 1 selection of csia0 serial clock (f scka division ratio) brgca0 6 0 5 0 4 0 3 0 2 0 1 brgc01 0 brgc00 after reset: 03h r/w address: fffffd43h 6 (f scka /6) 8 (f scka /8) 16 (f scka /16) 32 (f scka /32) (5) automatic data transfer address point specification register 0 (adtp0) this is an 8-bit register used to specify the buffe r ram address that ends transfer during automatic data transfer (csima0.ate0 bit = 1). this register can be read or written in 8-bit units. however, when the csis0.tsf0 bit is 1, rewriting the adtp0 register is prohibited. after reset, this register is cleared to 00h. in the v850es/kf1+, 00h to 1fh can be specified because 32 bytes of buffer ram are incorporated. example when the adtp0 register is set to 07h 8 bytes of fffffe00h to fffffe07h are transferred. in repeat transfer mode (csima0.atm0 bit = 1), trans fer is performed repeatedly up to the address value specified by the adtp0 register. example when the adtp0 register is set to 07h (repeat transfer mode) transfer is repeated as fffffe00h to fffffe07h, ? . 7 0 adtp0 6 0 5 0 4 adtp04 3 adtp03 2 adtp02 1 adtp01 0 adtp00 after reset: 00h r/w address: fffffd44h caution be sure to clear bits 5 to 7 to 0. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 488 the relationship between buffer ram address values and the adtp0 register setting values is shown below. table 17-2. relationship between buffer ram a ddress values and adtp0 register setting values buffer ram address value adtp0 register setting value b uffer ram address value adtp0 register setting value fffffe00h 00h fffffe10h 10h fffffe01h 01h fffffe11h 11h fffffe02h 02h fffffe12h 12h fffffe03h 03h fffffe13h 13h fffffe04h 04h fffffe14h 14h fffffe05h 05h fffffe15h 15h fffffe06h 06h fffffe16h 16h fffffe07h 07h fffffe17h 17h fffffe08h 08h fffffe18h 18h fffffe09h 09h fffffe19h 19h fffffe0ah 0ah fffffe1ah 1ah fffffe0bh 0bh fffffe1bh 1bh fffffe0ch 0ch fffffe1ch 1ch fffffe0dh 0dh fffffe1dh 1dh fffffe0eh 0eh fffffe1eh 1eh fffffe0fh 0fh fffffe1fh 1fh chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 489 (6) automatic data transfer inter val specification register 0 (adti0) this is an 8-bit register used to specify the interv al period between 1-byte trans fers during automatic data transfer (csima0.ate0 bit = 1). set this register when in master mode (csima0.mast er0 bit = 1) (setting is unnecessary in slave mode). setting in 1-byte transfer mode (ate0 bit = 0) is also va lid. when the interval ti me specified by the adti0 register after the end of 1-byte transfer has elapsed, a transmission/reception completion interrupt request signal (intcsia0) is output. the number of clocks for the interval can be set to between 0 and 63 clocks. this register can be read or written in 8-bit units. however, when the csis0.tsf0 bit is 1, rewriting the adti0 register is prohibited. after reset, this register is cleared to 00h. adti0 after reset: 00h r/w address: fffffd45h 7 0 6 0 5 adti05 4 adti04 3 adti03 2 adti02 1 adti01 0 adti00 the specified interval time is the transfer clock (specif ied by the brgca0 register) multiplied by an integer value. example when adti0 register = 03h scka0 interval time of 3 clocks (7) csia0 buffer ram (csia0bm) this area holds transmit/receive data (up to 32 byte s) in automatic transfer mode in 1-byte units. this register can be read or written in 16-bit units. however, when the higher 8 bits and the lower 8 bits of the csia0bm register are used as the csia0bmh r egister and csia0bml register, respectively, these registers can be read or written in 8-bit units. after automatic transfer is started, only data equal to one byte more than the number of bytes stored in the adtp0 register is transmitted/received in sequence from the csia0b0l register. cautions 1. to read the value of the csia0bm register after data is written to the register, wait for the duration of more than six clocks of f scka (serial clock set by the csis0.cksa01 and csis0.cksa00 bits) or until data is writte n to the buffer ram at another address. 2. when the main clock stops and th e cpu operates on the subclock, do not access the csia0bm register. for details, refer to 3.4.8 (2). remark m = 0 to f chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 490 table 17-3. csia0 buffer ram manipulatable bits address symbol r/w 8 16 after reset fffffe00h csia0b0 r/w undefined fffffe00h csia0b0l r/w undefined fffffe01h csia0b0h r/w undefined fffffe02h csia0b1 r/w undefined fffffe02h csia0b1l r/w undefined fffffe03h csia0b1h r/w undefined fffffe04h csia0b2 r/w undefined fffffe04h csia0b2l r/w undefined fffffe05h csia0b2h r/w undefined fffffe06h csia0b3 r/w undefined fffffe06h csia0b3l r/w undefined fffffe07h csia0b3h r/w undefined fffffe08h csia0b4 r/w undefined fffffe08h csia0b4l r/w undefined fffffe09h csia0b4h r/w undefined fffffe0ah csia0b5 r/w undefined fffffe0ah csia0b5l r/w undefined fffffe0bh csia0b5h r/w undefined fffffe0ch csia0b6 r/w undefined fffffe0ch csia0b6l r/w undefined fffffe0dh csia0b6h r/w undefined fffffe0eh csia0b7 r/w undefined fffffe0eh csia0b7l r/w undefined fffffe0fh csia0b7h r/w undefined fffffe10h csia0b8 r/w undefined fffffe10h csia0b8l r/w undefined fffffe11h csia0b8h r/w undefined fffffe12h csia0b9 r/w undefined fffffe12h csia0b9l r/w undefined fffffe13h csia0b9h r/w undefined fffffe14h csia0ba r/w undefined fffffe14h csia0bal r/w undefined fffffe15h csia0bah r/w undefined fffffe16h csia0bb r/w undefined fffffe16h csia0bbl r/w undefined fffffe17h csia0bbh r/w undefined fffffe18h csia0bc r/w undefined fffffe18h csia0bcl r/w undefined fffffe19h csia0bch r/w undefined fffffe1ah csia0bd r/w undefined fffffe1ah csia0bdl r/w undefined fffffe1bh csia0bdh r/w undefined fffffe1ch csia0be r/w undefined fffffe1ch csia0bel r/w undefined fffffe1dh csia0beh r/w undefined fffffe1eh csia0bf r/w undefined fffffe1eh csia0bfl r/w undefined fffffe1fh csia0bfh r/w undefined chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 491 17.4 operation csia0 can be used in the following two modes. ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function 17.4.1 3-wire serial i/o mode the one-byte data transmission/reception is executed in t he mode in which the csima0.ate0 bit is cleared to 0. in this mode, communication is executed by using three lin es: serial clock (scka0), serial data output (soa0), and serial data input (sia0) pins. the 3-wire serial i/o mode is controlled by the following three registers. ? serial operation mode specif ication register 0 (csima0) ? serial status register 0 (csis0) ? divisor selection register 0 (brgca0) remark for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions . chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 492 (1) 1-byte transmission/recep tion communication operation (a) 1-byte transmission/reception when the csima0.csiae0 bit and the csima0.ate0 bit = 1, 0, respectively, if transfer data is written to the sioa0 register, the data is out put via the soa0 pin in synchronization with the scka0 pin falling edge, and then input via the sia0 pin in synchroni zation with the falling edge of the scka0 pin, and stored in the sioa0 register in synchroniza tion with the rising edge 1 clock later. data transmission and data reception can be performed simultaneously. if only reception is to be performed, transfer can only be started by writing a dummy value to the sioa0 register. when transfer of 1 byte is complete, a transmission/reception completion interrupt request signal (intcsia0) is generated. in 1-byte transmission/reception, the se tting of the csima0.atm0 bit is invalid. be sure to read data after confi rming that the csis0.tsf0 bit = 0. caution determine the setting proc edure of alternate-function pins considering the relationship with the communication partner. figure 17-2. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end of transfer transfer starts at falling edge of scka0 pin scka0 sia0 soa0 intcsia0 sioa0 write tsf0 caution the soa0 pin becomes low l evel by the sioa0 register write. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 493 (b) data format in the data format, data is changed in synchronization with the scka0 pin falling edge as shown in figure 17-3. the data length is fixed to 8 bits and the data trans fer direction can be switched by the specification of the csima0.dira0 bit. figure 17-3. format of transmit/receive data (a) msb-first (dira0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dira0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7 chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 494 (c) switching msb/lsb as start bit figure 17-4 shows the configuration of the sioa0 register and the internal bus. as shown in the figure, msb/lsb can be read or written in reverse form. switching msb/lsb as the start bit can be specified using the csima0.dira0 bit. start bit switching is realized by switching the bit order for data written to the sioa0 register. the sioa0 register shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the sioa0 register. figure 17-4. transfer bit order switching circuit 7 6 internal bus 1 0 lsb-first msb-first read/write gate sia0 shift register 0 (sioa0) read/write gate soa0 scka0 dq soa0 latch (d) transfer start serial transfer is started by setting transfer data to the sioa0 register when the following two conditions are satisfied. ? csia0 operation control bit (csima0.csiae0) = 1 ? other than during serial communication caution if the csiae0 bit is set to 1 after data is written to the sioa 0 register, communication does not start. upon termination of 8-bit communication, serial communication automatically stops and the transmission/reception completion interrupt request signal (intcsia0) is generated. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 495 17.4.2 3-wire serial i/o mode with au tomatic transmit/receive function up to 32 bytes of data can be transmi tted/received without using software in the mode in which the csima0.ate0 bit is set to 1. after communication is started, only dat a of the set number of bytes stored in ram in advance can be transmitted, and only data of the set number of bytes can be received and stored in ram. the 3-wire serial i/o mode with automatic transmit/receive function is controlled by the following registers. ? serial operation mode specif ication register 0 (csima0) ? serial status register 0 (csis0) ? serial trigger register 0 (csit0) ? divisor selection register 0 (brgca0) ? automatic data transfer address point specification register 0 (adtp0) ? automatic data transfer interval specification register 0 (adti0) remark for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions . (1) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from t he least significant address ffff fe00h of buffer ram (up to fffffe1fh at maximum). the transmit data should be in the order from lo wer address to higher address. <2> set the adtp0 register to the value obtained by subtracting 1 from the number of transmit data bytes. (b) automatic transmissi on/reception mode setting <1> set the csima0.csiae0 bit and the csima0.ate0 bit to 11. <2> set the csima0.rxea0 bit a nd the csima0.txea0 bit to 11. <3> set a data transfer interval in the adti0 register. <4> set the csit0.atsta0 bit to 1. the following operations are automatically carried out when (a) and (b) are carried out. ? after the buffer ram data indicated by the adtc0 r egister (initial value: 00h) is transferred to the sioa0 register, transmission is carried out (s tart of automatic transmission/reception). ? the received data is written to the buffer ram address indicated by the adtc0 register. ? the adtc0 register is incremented and the next data transmission/reception is carried out. data transmission/reception continues until the adtc0 regist er incremental output matches the set value of the adtp0 register (end of automatic transmission/rec eption). however, if the csima0.atm0 bit is set to 1 (continuous transfer mode), the adtc0 regist er is cleared after a match between the adtp0 and adtc0 registers, and then repeated tr ansmission/reception is started. ? when automatic transmission/reception is termi nated, the csis0.tsf0 bit is cleared to 0. caution determine the setting proc edure of alternate-function pins considering the relationship with the communication partner. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 496 (2) automatic transmission/re ception communication operation (a) automatic transmi ssion/reception mode automatic transmission/reception can be performed using buffer ram. the data stored in the buffer ram is output from the soa0 pin via the sioa0 register in synchronization with the scka0 pin falling edge by performing (a) and (b) in (1) automatic transmit/receive data setting . the data is then input from the sia0 pin via the sioa 0 register in synchronization with the falling edge of the scka0 pin and the receive data is stored in the buffer ram in synchronization with the rising edge 1 clock later. data transfer ends if the csis0.tsf0 bit is cleared to 0 when any of the following conditions is met. ? reset by clearing the csima0.csiae0 bit to 0 ? transfer of 1 byte is complete by setting the csit0.atstp0 bit to 1 ? transfer of the range specified by the adtp0 register is complete at this time, a transmission/reception completion inte rrupt request signal (intcsia0) is generated except when the csiae0 bit = 0. if a transfer is terminated in the middle, transfer star ting from the remaining data is not possible. read the adtc0 register to confirm how much of the dat a has already been transferred, set the transfer data again, and perform (a) and (b) in (1) automatic transmit/receive data setting . figure 17-5 shows the operation timing in automatic transmission/reception mode and figure 17-6 shows the operation flowchart. figure 17-7 shows the oper ation of the buffer ram when 6 bytes of data are transmitted/received. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 497 figure 17-5. automatic transmission/reception mo de operation timings interval scka0 d7 soa0 sia0 intcsia0 tsf0 interval d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 cautions 1. because, in the automatic transmission/reception mode, the automatic transmit/receive function reads/writes da ta from/to the buffer ram after 1-byte transmission/reception, an inter val is inserted until the next transmission/reception. as the buffer ram read/write is performed at the same time as cpu processing, the interval is dependent upon the value of the adti0 register. 2. when the tsf0 bit is cleared , the soa0 pin becomes low level. 3. if cpu access to the buffer ram conflicts with csia0 read/write during the interval time, the inter val time becomes longer. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 498 figure 17-6. automatic transm ission/reception mode flowchart start write transmit data in buffer ram set adtp0 register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set automatic transmission/ reception mode set csit0.atsta0 bit to 1 write transmit data from buffer ram to sioa0 register transmission/reception operation write receive data from sioa0 register to buffer ram adtp0 register = adtc0 register no tsf0 bit = 0 no end yes yes increment pointer value software execution hardware execution software execution chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 499 in 6-byte transmission/reception (c sima0.atm0 bit = 0, csima0.rxea0 bit = 1, csima0.txea0 bit = 1) in automatic transmission/reception m ode, buffer ram operates as follows. (i) when transmission/reception operation is started (refer to figure 17-7 (a).) when the csit0.atsta0 bit is set to 1, transmit data 1 (t1) is transferred from the buffer ram to the sioa0 register. when transmission of the firs t byte is completed, receive data 1 (r1) is transferred from the sioa0 register to the buffer ram, and the adtc0 register is incremented. then transmit data 2 (t2) is transferred from the buffer ram to the sioa0 register. (ii) 4th byte transmission/reception point (refer to figure 17-7 (b).) transmission/reception of the third byte is complete d, and transmit data 4 (t4) is transferred from the buffer ram to the sioa0 register. when transmission of the fourth byte is completed, the receive data 4 (r4) is transferred from the sioa0 register to the buffer ram, and the value of the adtc0 register is incremented. (iii) completion of transmission/rece ption (refer to figure 17-7 (c).) when transmission of the sixth byte is completed, receive data 6 (r6) is transferred from the sioa0 register to the buffer ram, and the transmission/ reception completion interrupt request signal (intcsia0) is generated. figure 17-7. buffer ram operation in 6-byte transmission/reception (in automatic transmissi on/reception mode) (1/2) (a) when transmission/rece ption operation is started transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h receive data 1 (r1) sioa0 register not generated intcsia0 signal 0 adtc0 register +1 5 adtp0 register chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 500 figure 17-7. buffer ram operation in 6-byte transmission/reception (in automatic transmissi on/reception mode) (2/2) (b) 4th byte transmission/reception transmit data 6 (r6) transmit data 5 (r5) transmit data 4 (r4) receive data 3 (t3) receive data 2 (t2) receive data 1 (t1) fffffe1fh fffffe05h fffffe00h receive data 4 (r4) sioa0 register not generated intcsia0 signal 3 adtc0 register +1 5 adtp0 register (c) completion of transmission/reception receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) fffffe1fh fffffe05h fffffe00h sioa0 register generated intcsia0 signal 5 adtc0 register 5 adtp0 register chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 501 (b) automatic transmission mode in this mode, the specified number of 8-bit unit data are transmitted. serial transfer is started when the csit0.atst a0 bit is set to 1 while the csima0.csiae0, csima0.ate0, and csima0.txea0 bits are set to 1. when the final byte has been transmitted, an inte rrupt request signal (intcsia0) is generated. figure 17-8 shows the automatic transmission mode operation timing, and figure 17-9 shows the operation flowchart. figure 17-10 shows the operat ion of the buffer ram when 6 bytes of data are transmitted. figure 17-8. automatic transm ission mode operation timing interval scka0 d7 soa0 intcsia0 tsf0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval cautions 1. because, in the automatic transmission mode, th e automatic transmit/receive function reads data from the buffer ram a fter 1-byte transmission, an interval is inserted until the next transm ission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon the value of the adti0 register. 2. when the tsf0 bit is cleared , the soa0 pin becomes low level. 3. if cpu access to the buffer ram conflicts with csia0 read/write during the interval time, the inter val time becomes longer. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 502 figure 17-9. automatic tr ansmission mode flowchart start write transmit data in buffer ram set adtp0 register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set automatic transmission mode set csit0.atsta0 bit to 1 write transmit data from buffer ram to sioa0 register transmission operation adtp0 register = adtc0 register no tsf0 bit = 0 no end yes yes increment pointer value software execution hardware execution software execution chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 503 in 6-byte transmission (csima0.atm0 bit = 0, csima0.rxea0 bit = 0, csima0.txea0 bit = 1, csima0.ate0 bit = 1) in automatic transmission mode, buffer ram operates as follows. (i) when transmission is started (refer to figure 17-10 (a).) when the csit0.atsta0 bit is set to 1, transmit data 1 (t1) is transferred from the buffer ram to the sioa0 register. when transmission of the firs t byte is completed, the adtc0 register is incremented. then transmit data 2 (t2) is transfe rred from the buffer ram to the sioa0 register. (ii) 4th byte transm ission point (refer to figure 17-10 (b).) transmission of the third byte is completed, and transmit data 4 (t4) is transferred from the buffer ram to the sioa0 register. when transmission of t he fourth byte is completed, the value of the adtc0 register is incremented. (iii) completion of transmission (refer to figure 17-10 (c).) when transmission of the sixth byte is completed, the interrupt request signal (intcsia0) is generated, and the tfs0 flag is cleared to 0. figure 17-10. buffer ram operation in 6-byte transmission (in automatic transmission mode) (1/2) (a) when transmission is started transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioa0 register not generated intcsia0 signal 0 adtc0 register +1 5 adtp0 register chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 504 figure 17-10. buffer ram operation in 6-byte transmission (in automatic transmission mode) (2/2) (b) 4th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioa0 register not generated intcsia0 signal 3 adtc0 register +1 5 adtp0 register (c) completion of transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioa0 register generated intcsia0 signal 5 adtc0 register 5 adtp0 register chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 505 (c) repeat transmission mode in this mode, data stored in the buffer ram is transmitted repeatedly. serial transfer is started when the csit0.atst a0 bit is set to 1 while the csima0.csiae0, csima0.ate0, csima0.atm0, and csima0.txea0 bits are set to 1. unlike the basic transmission mode, after the spec ified number of bytes has been transmitted, the transmission/reception completion interrupt request si gnal (intcsia0) is not generated, the adtc0 register is reset to 0, and the buffe r ram contents are transmitted again. the repeat transmission mode operation timing is shown in figure 17-11, and the operation flowchart in figure 17-12. figure 17-13 shows the operation of the buffer ram w hen 6 bytes of data are transmitted in the repeat transmission mode. figure 17-11. repeat transmission mode operation timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 scka0 soa0 cautions 1. because, in the repeat transmi ssion mode, a read is performed on the buffer ram after the transmission of one byte, th e interval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is depe ndent upon the value of the adti0 register. 2. if cpu access to the buffer ram conflicts with csia0 read/write during the interval time, the inter val time becomes longer. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 506 figure 17-12. repeat transmission mode flowchart start write transmit data in buffer ram set adtp0 register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set repeat transmission mode set csit0.atsta0 bit to 1 write transmit data from buffer ram to sioa0 register transmission operation adtp0 register = adtc0 register no yes increment pointer value software execution hardware execution reset adtc0 register to 0 chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 507 in 6-byte transmission (csima0.atm0 bit = 1, csima0.rxea0 bit = 0, csima0.txea0 bit = 1, csima0.ate0 bit = 1) in repeat transmission mode, buffer ram operates as follows. (i) when transmission is started (refer to figure 17-13 (a).) when the csit0.atsta0 bit is set to 1, transmit data 1 (t1) is transferred from the buffer ram to the sioa0 register. when transmission of the firs t byte is completed, the value of the adtc0 register is incremented. then transmit data 2 (t2) is transferred from the buffer ram to the sioa0 register. (ii) upon completion of transmission of 6 bytes (refer to figure 17-13 (b).) when transmission of the sixth byte is completed, the interrupt request signal (intcsia0) is not generated. the adtc0 register is reset to 0. (iii) 7th byte transmission poin t (refer to figure 17-13 (c).) transmit data 1 (t1) is transferred from the bu ffer ram to the sioa0 register again. when transmission of the first byte is completed, the va lue of the adtc0 register is incremented. then transmit data 2 (t2) is transferred from the buffer ram to the sioa0 register. figure 17-13. buffer ram operation in 6-byte transmission (in repeat transmission mode) (1/2) (a) when transmission is started transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioa0 register not generated intcsia0 signal 0 adtc0 register +1 5 adtp0 register chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 508 figure 17-13. buffer ram operation in 6-byte transmission (in repeat transmission mode) (2/2) (b) upon completion of transmission of 6 bytes transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioa0 register not generated intcsia0 signal 5 adtc0 register 5 adtp0 register (c) 7th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fffffe1fh fffffe05h fffffe00h sioa0 register not generated intcsia0 signal 0 adtc0 register +1 5 adtp0 register chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 509 (d) data format in the data format, data is changed in synchronization with the scka0 pin falling edge as shown in figure 17-14. the data length is fixed to 8 bits and the data trans fer direction can be switched by the specification of the csima0.dira0 bit. figure 17-14. format of csia0 transmit/receive data (a) msb-first (dira0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dira0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7 chapter 17 clocked serial interface a (csia) with automatic transmit/receive function preliminary user?s manual u16895ej1v0ud 510 (e) automatic transmission/rece ption suspension and restart automatic transmission/reception can be temporarily suspended by setting the csit0.atstp0 bit to 1. during 8-bit data transfer, the transmission/reception is not suspended. it is suspended upon completion of 8-bit data transfer. when suspended, the csis0.tsf0 bit is cleared to 0 after transfer of the 8th bit. to restart automatic transmission/rec eption, set the csit0.atsta0 bit to 1. the remaining data can be transmitted in this way. cautions 1. if the idle instruction is executed during automatic transmissi on/reception, transfer is suspended and the idle mode is set if during 8-bit data transfer. when the idle mode is cleared, automatic transmission/ reception is restarted from the suspended point. 2. when suspending automa tic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while the tsf0 bit = 1. figure 17-15. automatic transmissi on/reception suspension and restart scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command atsta0 bit = 1 suspend atstp0 bit = 1 (suspend command) preliminary user?s manual u16895ej1v0ud 511 chapter 18 i 2 c bus to use the i 2 c bus function, set the p38/sda0 and p39/scl0 pins to n-ch open drain output as the alternate function. in the v850es/kf1+, one channel of i 2 c bus is provided. the products with an on-chip i 2 c bus are shown below. pd703308y, 70f3306y, 70f3308y 18.1 features the i 2 c0 has the following two modes. operation stop mode i 2 c (inter ic) bus mode (multimaster supported) (1) operation stop mode this mode is used when serial transfers are not per formed. it can therefor e be used to reduce power consumption. (2) i 2 c bus mode (multi master supported) this mode is used for 8-bit data transfers with several dev ices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. this mode complies with the i 2 c bus format and the master device can output ?start condition?, ?data?, and ?stop condition? data to the slave devic e, via the serial data bus. the slav e device automatica lly detects these received data by hardware. this f unction can simplify the part of applicat ion program that controls the i 2 c bus. since the scl0 and sda0 pins are used for n-ch open drain outputs, i 2 c0 requires pull-up resistors for the serial clock line and the serial data bus line. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 512 figure 18-1. block diagram of i 2 c0 iice0 dq cl01, cl00 sda0 scl0 intiic0 f xx lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 cld0 dad0 smc0 dfc0 cl01 cl00 clx0 stcf0 iicbsy0 stcen0 iicrsv0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator match signal iic shift register 0 (iic0) so latch set clear n-ch open- drain output n-ch open- drain output data hold time correction circuit ack output circuit wakeup controller ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler start condition detector internal bus iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) iic flag register 0 (iicf0) start condition generator bus status detector chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 513 a serial bus configuration example is shown below. figure 18-2. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2 chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 514 18.2 configuration i 2 c0 includes the following hardware. table 18-1. configuration of i 2 c0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iiccf0) iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) (1) iic shift register 0 (iic0) the iic0 register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8- bit serial data. the iic0 register can be used for both transmission and reception. write and read operations to the iic0 r egister are used to control the act ual transmit and receive operations. the iic0 register can be read or written in 8-bit units. after reset, iic0 is cleared to 00h. (2) slave address register 0 (sva0) the sva0 register sets local addresses when in slave mode. the sva0 register can be read or written in 8-bit units. after reset, sva0 is cleared to 00h. (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wakeup controller this circuit generates an interrupt r equest signal (intiic0) when the address re ceived by this register matches the address value set to the sva0 register or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt is generated by the following two triggers. ? falling edge of the eighth or ninth clock of t he serial clock (set by iicc0.wtim0 bit) ? interrupt request generated when a stop condition is detected (set by iicc0.spie0 bit) chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 515 (8) serial clock controller in master mode, this circuit generates the clo ck output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector , start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start condition when the iicc0.stt0 bit is set. however, in the communication reservation disabled st atus (iicf0.iicrsv0 bit = 1), when the bus is not released (iicf0.iicbsy0 bit = 1), start condition requests are ignored and the iicf0.stcf0 bit is set to 1. (13) bus status detector this circuit detects whether or not the bus is rel eased by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediatel y following operation, the init ial status is set by the iicf0.stcen0 bit. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 516 18.3 registers i 2 c0 is controlled by the following registers. iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iicf0) iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) the following registers are also used. iic shift register 0 (iic0) slave address register 0 (sva0) remark for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions . (1) iic control register 0 (iicc0) the iicc0 register is used to enable/stop i 2 c0 operations, set wait timing, and set other i 2 c operations. the iicc0 register can be read or written in 8-bit or 1-bit units. after reset, iicc0 is cleared to 00h. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 517 (1/4) after reset: 00h r/w address: fffffd82h <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c0 operation enable/dis able specification 0 stop operation. reset the iics0 register note 1 . stop internal operation. 1 enable operation. condition for clearing (iice0 bit = 0) condition for setting (iice0 bit = 1) ? cleared by instruction ? reset ? set by instruction lrel0 exit from communications 0 normal operation 1 this exits from the current communications and sets standby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines are set to high impedance. the stt0, spt0, iics0.msts0, iics0.exc0, iics0.coi 0, iics0.trc0, iics0.ackd0, and iics0.std0 bits are cleared to 0. the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rec eption occurs after the start condition. condition for clearing (lrel0 bit = 0) note 2 condition for setting (lrel0 bit = 1) ? automatically cleared after execution ? reset ? set by instruction wrel0 wait cancellation control 0 do not cancel wait 1 cancel wait. this setting is automatica lly cleared to 0 after wait is canceled. condition for clearing (wrel0 bit = 0) note 2 condition for setting (wrel0 bit = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics0 register, and the iicf0.stcf0, iicf0 .iicbsy0, iiccl0.cld0, and iiccl0.dad0 bits are reset. 2. this flag?s signal is invalid when the iice0 bit = 0. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 518 (2/4) spie0 enable/disable generation of interr upt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 bit = 0) note condition for setting (spie0 bit = 1) ? cleared by instruction ? reset ? set by instruction wtim0 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. the setting of this bit is valid when the address transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. fo r a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an a cknowledge signal (ack) is issued. however, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 bit = 0) note condition for setting (wtim0 bit = 1) ? cleared by instruction ? reset ? set by instruction acke0 acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during the nint h clock period, the sda0 line is set to low level. however, ack is invalid during address transfers and other than in expansion mode. condition for clearing (acke0 bit = 0) note condition for setting (acke0 bit = 1) ? cleared by instruction ? reset ? set by instruction note this flag?s signal is invalid when the iice0 bit = 0. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 519 (3/4) stt0 start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). the sda0 line is changed from high level to low level and then the start condition is generated. next, afte r the rated amount of time has elapsed, the scl0 line is changed to low level. when a third party is communicating: ? when communication reservation functi on is enabled (iicf0.iicrsv0 bit = 0) functions as the start condition reservation flag. when set to 1, automatically generates a start condition after the bus is released. ? when communication reservation functi on is disabled (iicrsv0 bit = 1) the iicf0.stcf0 bit is set to 1. no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acke0 bit has been cleared to 0 and slave has been notified of final reception. for master transmission: a start condition cannot be generated normally during the ack0 period. set to 1 during the wait period. ? cannot be set to 1 at the same time as the spt0 bit. condition for clearing (stt0 bit = 0) note condition for setting (stt0 bit = 1) ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when the lrel0 bit = 1 (e xit from communications) ? when the iice0 bit = 0 (operation stop) ? reset ? set by instruction note this flag?s signal is invalid when the iice0 bit = 0. remark the stt0 bit is 0 if it is read after data setting. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 520 (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until the scl0 pin goes to high level. next, after the rated amount of time has elapsed, the sda0 line is changed from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acke0 bit has been cleared to 0 and during the wait period after slave has been notified of final reception. for master transmission: a stop condition cannot be generat ed normally during the ack signal period. set to 1 during the wait period. ? cannot be set to 1 at the same time as the stt0 bit. the spt0 bit can be set to 1 only when in master mode note 1 . when the wtim0 bit has been cleared to 0, if the spt0 bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generat ed during the high-level period of the ninth clock. when a ninth clock must be output, the wtim0 bit should be set from 0 to 1 during the wait period following output of eight clocks, and the spt0 bit should be set to 1 during the wait period that follows output of the ninth clock. condition for clearing (spt0 bit = 0) note 2 condition for setting (spt0 bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lrel0 bit = 1 (e xit from communications) ? when the iice0 bit = 0 (operation stop) ? reset ? set by instruction notes 1. set the spt0 bit to 1 only in master mode. however, the spt0 bit must be set to 1 and a stop condition generated befor e the first stop condition is det ected following the switch to operation enable status. for details, refer to 18.14 cautions . 2. this flag?s signal is invalid when the iice0 bit = 0. caution when the iics0.trc0 bit is set to 1, th e wrel0 bit is set to 1 during the ninth clock and wait is canceled, after which the trc0 bi t is cleared to 0 and the sda0 line is set to high impedance. remark the spt0 bit is 0 if it is read after data setting. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 521 (2) iic status register 0 (iics0) the iics0 register indica tes the status of the i 2 c0 bus. the iics0 register is read-only, in 8-bit or 1-bit units. after reset, iics0 is cleared to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the iics0 register using an access method that causes a wait. for details, refer to 3.4.8 (2). (1/3) after reset: 00h r address: fffffd86h <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 bit = 0) condition for setting (msts0 bit = 1) ? when a stop condition is detected ? when the ald0 bit = 1 (arbitration loss) ? cleared by the iicc0.lrel0 bit = 1 (exit from communications) ? when the iicc0.iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald0 detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the msts0 bit is cleared to 0. condition for clearing (ald0 bit = 0) condition for setting (ald0 bit = 1) ? automatically cleared after the iics0 register is read note ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. note this register is also cleared when a bit manipulation instruction is executed for bits other than the iics0 register. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 522 (2/3) exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 bit = 0) condition for setting (exc0 bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (s et at the rising edge of the eighth clock). coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 bit = 0) condition for setting (coi0 bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the received address matches the local address (sva0 register) (set at the rising edge of the eighth clock). trc0 detection of transmit/receive status 0 receive status (other than transmit status ). the sda0 line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sda0 line (valid starting at the rising edge of the first byte?s ninth clock). condition for clearing (trc0 bit = 0) condition for setting (trc0 bit = 1) ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? cleared by the iicc0.wrel0 bit = 1 note (wait release) ? when the ald0 bit changes from 0 to 1 (arbitration loss) ? reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated slave ? when ?1? is input in the first byte?s lsb (transfer direction specification bit) note the trc0 bit is cleared to 0 and the sda0 li ne becomes high impedance when the wrel0 bit is set to 1 and wait state is released at t he ninth clock with the trc0 bit = 1. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 523 (3/3) ackd0 detection of acknowledge signal (ack) 0 ack signal was not detected. 1 ack signal was detected. condition for clearing (ackd0 bit = 0) condition for setting (ackd0 bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? after the sda0 pin is set to low level at the rising edge of the scl0 pin?s ninth clock std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std0 bit = 0) condition for setting (std0 bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spd0 bit = 0) condition for setting (spd0 bit = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 524 (3) iic flag register 0 (iicf0) iicf0 is a register that sets the operation mode of i 2 c0 and indicates the status of the i 2 c bus. this register can be read or written in 8-bit or 1-bit units. however, the stcf0 and iicbsy0 bits are read-only. the iicrsv0 bit can be used to enable/disable t he communication reservation function (refer to 18.13 communication reservation ). the stcen0 bit can be used to set the in itial value of the iicbsy0 bit (refer to 18.14 cautions ). the iicrsv0 and stcen0 bits can be written only when the operation of i 2 c0 is disabled (iicc0.iice0 bit = 0). when operation is enabled, the iic f0 register can be read. after reset, iicf0 is cleared to 00h. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 525 <7> stcf0 condition for clearing (stcf0 bit = 0) cleared by the stt0 bit = 1 reset condition for setting (stcf0 bit = 1) generating start condition unsuccessful and the stt0 bit cleared to 0 when communication reservation is disabled (iicrsv0 bit = 1). stcf0 0 1 generate start condition start condition generation unsuccessful: clear stt0 flag stt0 clear flag iicf0 <6> iicbsy0 5 0 4 0 3 0 2 0 <1> stcen0 <0> iicrsv0 after reset: 00h r/w note address: fffffd8ah condition for clearing (iicbsy0 bit = 0) detection of stop condition reset condition for setting (iicbsy0 bit = 1) detection of start condition setting of the iice0 bit when the stcen0 bit = 0 iicbsy0 0 1 bus release status bus communication status i 2 c0 bus status flag condition for clearing (stce0 bit = 0) detection of start condition reset condition for setting (stce0 bit = 1) setting by instruction stcen0 0 1 after operation is enabled (iice0 bit = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice0 bit = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv0 bit = 0) cleared by instruction reset condition for setting (iicrsv0 bit = 1) setting by instruction iicrsv0 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only bits. cautions 1. write to the stcen0 bit only wh en the operation is stopped (iice0 bit = 0). 2. as the bus release status (iicbsy0 bit = 0) is recognized regardless of the actual bus status when the stcen0 bit = 1, when gene rating the first start condition (stt0 bit = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. write to the iicrsv0 bit only when the operation is stopped (iice0 bit = 0). chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 526 (4) iic clock selection register 0 (iiccl0) the iiccl0 register is used to set the transfer clock for i 2 c0. the iiccl0 register can be r ead or written in 8-bit or 1-bit units. however, the cld0 and dad0 bits are read- only. the smc0, cl01, and cl00 bits are set in combination with the iicx0.clx0 bit (refer to 18.3 (6) i 2 c0 transfer clock setting method ). after reset, iiccl0 is cleared to 00h. after reset: 00h r/w note address: fffffd84h 7 6 <5> <4> 3 2 1 0 iiccl0 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 cld0 detection of scl0 pin level (valid only when iicc0.iice0 bit = 1) 0 the scl0 pin was detected at low level. 1 the scl0 pin was detected at high level. condition for clearing (cld0 bit = 0) condition for setting (cld0 bit = 1) ? when the scl0 pin is at low level ? when the iice0 bit = 0 (operation stop) ? reset ? when the scl0 pin is at high level dad0 detection of sda0 pin level (valid only when iice0 bit = 1) 0 the sda0 pin was detected at low level. 1 the sda0 pin was detected at high level. condition for clearing (dad0 bit = 0) condition for setting (dad0 bit = 1) ? when the sda0 pin is at low level ? when the iice0 bit = 0 (operation stop) ? reset ? when the sda0 pin is at high level smc0 operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfc0 digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfc0 bit set/clear. the digital filter is used for noi se elimination in high-speed mode. note bits 4 and 5 are read-only bits. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 527 (5) iic function expansion register 0 (iicx0) this register sets the function expansion of i 2 c0 (valid only in high-speed mode). this register can be read or written in 8-bit or 1-bit units. the clx0 bit is set in combination with the iiccl0.smc0, iiccl0.cl01, and iiccl0.cl00 bits (refer to 18.3 (6) i 2 c0 transfer clock setting method ). after reset, iicx0 is cleared to 00h. after reset: 00h r/w address: fffffd85h 7 6 5 4 3 2 1 <0> iicx0 0 0 0 0 0 0 0 clx0 (6) i 2 c0 transfer clock setting method the i 2 c0 transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 12, 24, 48, 54, 86, 88, 172, 198 (refer to table 18-2 selection clock setting ) t: 1/f xx t r : scl0 rise time t f : scl0 fall time for example, the i 2 c0 transfer clock frequency (f scl ) when f xx = 16 mhz, m = 172, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(172 62.5 ns + 200 ns + 50 ns) ? 90.9 khz m t + t r + t f m/2 t t f t r m/2 t scl0 scl0 inversion scl0 inversion scl0 inversion the selection clock is set using a combination of the iiccl0.smc0, iiccl0.cl01, and iiccl0.cl00 bits and the iicx0.clx0 bit. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 528 table 18-2. selection clock setting iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock transfer clock (f xx /m) settable internal system clock frequency (f xx ) range operation mode 0 0 0 0 f xx /2 f xx /88 4.0 mhz to 8.38 mhz 0 0 0 1 f xx /2 f xx /172 8.38 mhz to 16.76 mhz 0 0 1 0 f xx f xx /86 4.19 mhz to 8.38 mhz 0 0 1 1 f xx /3 f xx /198 16.0 mhz to 19.8 mhz normal mode (smc0 bit = 0) 0 1 0 x f xx /2 f xx /48 8 mhz to 16.76 mhz 0 1 1 0 f xx f xx /24 4 mhz to 8.38 mhz 0 1 1 1 f xx/ 3 f xx /54 16 mhz to 20 mhz high-speed mode (smc0 bit = 1) 1 0 x x setting prohibited 1 1 0 x f xx /2 f xx /24 8.00 mhz to 8.38 mhz 1 1 1 0 f xx f xx /12 4.00 mhz to 4.19 mhz high-speed mode (smc0 bit = 1) 1 1 1 1 setting prohibited remark x: don?t care (7) iic shift register 0 (iic0) the iic0 register is used for serial transmission/reception (shift operations) t hat is synchronized with the serial clock. the iic0 register can be read or writt en in 8-bit units, but data should not be written to the iic0 register during a data transfer. when the iic0 register is written during wait, the wait is cancelled and dat a transfer is started. after reset, iic0 is cleared to 00h. after reset: 00h r/w address: fffffd80h 7 6 5 4 3 2 1 0 iic0 (8) slave address register 0 (sva0) the sva0 register holds the i 2 c bus?s slave addresses. the sva0 register can be read or written in 8-bit units, but bit 0 should be fixed as 0. after reset, sva0 is cleared to 00h. after reset: 00h r/w address: fffffd83h 7 6 5 4 3 2 1 0 sva0 0 chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 529 18.4 functions 18.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. scl0 .............. this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sda0 .............. this pi n is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial dat a bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 18-3. pin configuration diagram v dd scl0 sda0 scl0 sda0 v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 530 18.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition?, ?data?, and ?stop conditi on? output via the i 2 c bus?s serial data bus is shown below. figure 18-4. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scl0 sda0 start condition address r/w ack data data stop condition ack ack the master device outputs t he start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave dev ice (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master devic e. however, in the sl ave device, the scl0 pin?s low-level period can be extended and a wait can be inserted. 18.5.1 start condition a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are si gnals that the master device outputs to the slave device when starting a serial transfer. start conditions can be detected when the devic e is used as a slave. figure 18-5. start conditions h scl0 sda0 a start condition is output when the iicc0.stt0 bit is se t to 1 after a stop condition has been detected (iics0.spd0 bit = 1). when a start condition is detec ted, the iics0.std0 bit is set to 1. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 531 18.5.2 addresses the 7 bits of data that follow the st art condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via bus lines. t herefore, each slave devic e connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and che cks whether or not the 7-bit address data matches the data values stored in the sva0 register. if the address data matches the sva0 register values, the slave device is selected and communicate s with the master device until the mast er device transmits a start condition or stop condition. figure 18-6. address address scl0 1 sda0 intiic0 note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (int iic0) is generated if a local addre ss or extension code is received during slave device operation. the slave address and the eighth bit, which specif ies the transfer direction as described in 18.5.3 transfer direction specification below, are together written to the iic0 regi ster and are then output. received addresses are written to the iic0 register. the slave address is assigned to the hi gher 7 bits of the iic0 register. 18.5.3 transfer di rection specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfe r direction. when this transfer direction specification bit has a value of 0, it indicates that the mast er device is transmitting data to a slave device. when the transfer direction specif ication bit has a value of 1, it indica tes that the master device is receiving data from a slave device. figure 18-7. transfer direction specification scl0 1 sda0 intiic0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the interrupt request signal (int iic0) is generated if a local addre ss or extension code is received during slave device operation. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 532 18.5.4 acknowledge signal (ack) the acknowledge signal (ack) is used by the transmitting and re ceiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. t he transmitting device normally receives an ack signal after transmitting 8 bits of data. ho wever, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the trans mitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave dev ice does not return an ack signal, the master device outputs either a stop condition or a rest art condition and then stops the current tr ansmission. failure to return an ack signal may be caused by the following two factors. <1> reception was not performed normally. <2> the final data was received. when the receiving device sets the sda0 line to low leve l during the ninth clock, t he ack signal becomes active (normal receive response). when the iicc0.acke0 bit is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes the iics0.trc0 bit to be set. when this trc0 bit?s value is 0, it indicates receive mode. therefore, the acke0 bit should be set to 1. when the slave device is receiving (when trc0 bit = 0), if the slave device does not need to receive any more data after receiving several bytes, clearing the acke0 bit to 0 will prevent the mast er device from starting transmission of the subsequent data. similarly, when the master device is receiving (w hen trc0 bit = 0) and the subsequent data is not needed and when either a restart condition or a st op condition should therefore be output, cl earing the acke0 bit to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sda0 line (i.e., stops transmission) during transmissi on from the slave device. figure 18-8. acknowledge signal (ack) scl0 1 sda0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack when the local address is received, an ack signal is aut omatically output in synch ronization with the falling edge of the scl0 pin?s eighth clock regardless of the acke0 bit va lue. no ack signal is output if the received address is not a local address. the ack signal output method during dat a reception is based on the wait timing setting, as described below. ? when 8-clock wait is selected: ack signal is output at the falling edge of the scl0 pin?s eighth clock if the (iicc0.wtim0 bit = 0) acke0 bit is set to 1 before wait cancellation. ? when 9-clock wait is selected: ack signal is automat ically output at the falling edge of the scl0 pin?s eighth (wtim0 bit = 1) clock if the acke0 bit has already been set to 1. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 533 18.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that t he master device outputs to the slav e device when serial transfer has been completed. stop conditions can be detect ed when the device is used as a slave. figure 18-9. stop condition h scl0 sda0 a stop condition is generated when the ii cc0.spt0 bit is set to 1. when the stop condition is detected, the iics0.spd0 bit is set to 1 and the interrupt request signal (i ntiic0) is generated when the iicc0 .spie0 bit is set to 1. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 534 18.5.6 wait signal (wait) the wait signal (wait) is used to notif y the communication partner that a devic e (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave dev ices, the next data transfer can begin. figure 18-10. wait signal (1/2) (a) when master device has a nine-clock wa it and slave device has an eight-clock wait (master: transmission, slave: reception, and iicc0.acke0 bit = 1) scl0 6 sda0 78 9 123 scl0 iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iic0 data write (cancel wait) slave wait after output of eighth clock. ffh is written to iic0 register or iicc0.wrel0 bit is set to 1. transfer lines wait signal from slave wait signal from master chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 535 figure 18-10. wait signal (2/2) (b) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acke0 bit = 1) scl0 6 sda0 789 123 scl0 iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master and slave both wait after output of ninth clock. iic0 data write (cancel wait) slave ffh is written to iic0 register or wrel0 bit is set to 1. output according to previously set acke0 bit value transfer lines wait signal from master and slave wait signal from slave a wait may be automatically generated depending on the setting for the iicc0.wtim0 bit. normally, when the wrel0 bit is set to 1 or when ffh is wr itten to the iic0 register, t he wait status is canceled and the transmitting side writes data to the iic 0 register to cancel the wait status. the master device can also c ancel the wait status via ei ther of the following methods. by setting the iicc0.stt0 bit to 1 by setting the iicc0.spt0 bit to 1 chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 536 18.6 i 2 c interrupt request signals (intiic0) the following shows the value of the iic s0 register at the intiic0 interr upt request signal generation timing and at the intiic0 signal timing. 18.6.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iicc0.wtim0 bit = 0 iicc0.spt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 10xxx110b 2: iics0 register = 10xxx000b 3: iics0 register = 10xxx000b (wtim0 bit = 1) 4: iics0 register = 10xxxx00b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 spt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 10xxx110b 2: iics0 register = 10xxx100b 3: iics0 register = 10xxxx00b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 537 (2) start ~ address ~ data ~ star t ~ address ~ data ~ stop (restart) <1> when wtim0 bit = 0 iicc0.stt0 bit = 1 spt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iics0 register = 10xxx110b 2: iics0 register = 10xxx000b (wtim0 bit = 1) 3: iics0 register = 10xxxx00b (wtim0 bit = 0) 4: iics0 register = 10xxx110b (wtim0 bit = 0) 5: iics0 register = 10xxx000b (wtim0 bit = 1) 6: iics0 register = 10xxxx00b ? 7: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 stt0 bit = 1 spt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 10xxx110b 2: iics0 register = 10xxxx00b 3: iics0 register = 10xxx110b 4: iics0 register = 10xxxx00b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 538 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtim0 bit = 0 spt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 1010x110b 2: iics0 register = 1010x000b 3: iics0 register = 1010x000b (wtim0 bit = 1) 4: iics0 register = 1010xx00b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 spt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 1010x110b 2: iics0 register = 1010x100b 3: iics0 register = 1010xx00b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 539 18.6.2 slave device operation (when receiving slave address da ta (match with address)) (1) start ~ address ~ data ~ data ~ stop <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0001x110b 2: iics0 register = 0001x000b 3: iics0 register = 0001x000b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0001x110b 2: iics0 register = 0001x100b 3: iics0 register = 0001xx00b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 540 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 0001x110b 2: iics0 register = 0001x000b 3: iics0 register = 0001x110b 4: iics0 register = 0001x000b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 0001x110b 2: iics0 register = 0001xx00b 3: iics0 register = 0001x110b 4: iics0 register = 0001xx00b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 541 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtim0 bit = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 0001x110b 2: iics0 register = 0001x000b 3: iics0 register = 0010x010b 4: iics0 register = 0010x000b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iics0 register = 0001x110b 2: iics0 register = 0001xx00b 3: iics0 register = 0010x010b 4: iics0 register = 0010x110b 5: iics0 register = 0010xx00b ? 6: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 542 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0001x110b 2: iics0 register = 0001x000b 3: iics0 register = 00000x10b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0001x110b 2: iics0 register = 0001xx00b 3: iics0 register = 00000x10b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 543 18.6.3 slave device operation (w hen receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0010x010b 2: iics0 register = 0010x000b 3: iics0 register = 0010x000b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 0010x010b 2: iics0 register = 0010x110b 3: iics0 register = 0010x100b 4: iics0 register = 0010xx00b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 544 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 0010x010b 2: iics0 register = 0010x000b 3: iics0 register = 0001x110b 4: iics0 register = 0001x000b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iics0 register = 0010x010b 2: iics0 register = 0010x110b 3: iics0 register = 0010xx00b 4: iics0 register = 0001x110b 5: iics0 register = 0001xx00b ? 6: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 545 (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtim0 bit = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 0010x010b 2: iics0 register = 0010x000b 3: iics0 register = 0010x010b 4: iics0 register = 0010x000b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iics0 register = 0010x010b 2: iics0 register = 0010x110b 3: iics0 register = 0010xx00b 4: iics0 register = 0010x010b 5: iics0 register = 0010x110b 6: iics0 register = 0010xx00b ? 7: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 546 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0010x010b 2: iics0 register = 0010x000b 3: iics0 register = 00000x10b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 0010x010b 2: iics0 register = 0010x110b 3: iics0 register = 0010xx00b 4: iics0 register = 00000x10b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 547 18.6.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? 1 ? 1: iics0 register = 00000001b remark ? : generated only when iicc0.spie0 bit = 1 18.6.5 arbitration loss operation (ope ration as slave after arbitration loss) (1) when arbitration loss occurs duri ng transmission of slave address data <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0101x110b (example: when iics0 .ald0 bit is read during interrupt servicing) 2: iics0 register = 0001x000b 3: iics0 register = 0001x000b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0101x110b (example: when al d0 bit is read during in terrupt servicing) 2: iics0 register = 0001x100b 3: iics0 register = 0001xx00b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 548 (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 0110x010b (example: when al d0 bit is read during interrupt servicing) 2: iics0 register = 0010x000b 3: iics0 register = 0010x000b ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iics0 register = 0110x010b (example: when al d0 bit is read during interrupt servicing) 2: iics0 register = 0010x110b 3: iics0 register = 0010x100b 4: iics0 register = 0010xx00b ? 5: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 549 18.6.6 operation when arbitr ation loss occurs (no communicat ion after arbitration loss) (1) when arbitration loss occurs dur ing transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iics0 register = 01000110b (example: when iics0 .ald0 bit is read during interrupt servicing) ? 2: iics0 register = 00000001b remark : always generated ? : generated only when iicc0.spie0 bit = 1 (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iics0 register = 0110x010b (example: when al d0 bit is read during interrupt servicing) iicc0.lrel0 bit is set to 1 by software ? 2: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 550 ( 3) when arbitration loss occurs during data transfer <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iics0 register = 10001110b 2: iics0 register = 01000000b (example: when al d0 bit is read during interrupt servicing) ? 3: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 <2> when wtim0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iics0 register = 10001110b 2: iics0 register = 01000100b (example: when al d0 bit is read during interrupt servicing) ? 3: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 551 (4) when loss occurs due to rest art condition during data transfer <1> not extension code (example: mismatches with address) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iics0 register = 1000x110b 2: iics0 register = 01000110b (example: when al d0 bit is read during interrupt servicing) ? 3: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care dn = d6 to d0 <2> extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iics0 register = 1000x110b 2: iics0 register = 0110x010b (example: when al d0 bit is read during interrupt servicing) lrel0 bit is set to 1 by software ? 3: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care dn = d6 to d0 chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 552 (5) when loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dn sp 1 ? 2 1: iics0 register = 1000x110b ? 2: iics0 register = 01000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care dn = d6 to d0 (6) when arbitration loss occurs due to low-level da ta when attempting to gene rate a restart condition when wtim0 bit = 1 iicc0.stt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 1000x110b 2: iics0 register = 1000xx00b 3: iics0 register = 01000100b (example: when al d0 bit is read during interrupt servicing) ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 553 (7) when arbitration loss occurs due to a stop conditi on when attempting to gene rate a restart condition when wtim0 bit = 1 stt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iics0 register = 1000x110b 2: iics0 register = 1000xx00b ? 3: iics0 register = 01000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care (8) when arbitration loss occurs due to low-level data when attemp ting to generate a stop condition when wtim0 bit = 1 iicc0.spt0 bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iics0 register = 1000x110b 2: iics0 register = 1000xx00b 3: iics0 register = 01000000b (example: when al d0 bit is read during interrupt servicing) ? 4: iics0 register = 00000001b remark : always generated ? : generated only when spie0 bit = 1 x: don?t care chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 554 18.7 interrupt request signal (intiic0) generation timing and wait control the setting of the iicc0.wtim0 bit determines the ti ming by which the intiic 0 signal is generated and the corresponding wait control, as shown below. table 18-3. intiic0 signal gene ration timing and wait control during slave device operation du ring master device operation wtim0 bit address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic0 signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the addre ss set to the sva0 register. at this point, an ack signal is output regardless of the value set to the iicc0.acke0 bit. for a slave device that has received an extensi on code, the intiic0 signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the intiic0 signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not ma tch the contents of the sva0 regi ster and extensi on codes have not been received, neither the intiic0 signal nor a wait occurs. remark the numbers in the table indicate the number of the serial clock?s cl ock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined depending on the conditions in notes 1 and 2 above regardless of the wtim0 bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 555 (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting the iicc0.wrel0 bit to 1 ? by writing to the iic0 register ? by start condition setting (iicc0.stt0 bit = 1) note ? by stop condition setting (iicc0.spt0 bit = 1) note note master only when an 8-clock wait has been selected (wtim0 bit = 0), the output level of the ack signal must be determined prior to wait cancellation. (5) stop condition detection the intiic0 signal is generated w hen a stop condition is detected. 18.8 address match detection method when in i 2 c bus mode, the master device c an select a particular slave device by transmitting the corresponding slave address. address match detection is performed autom atically by hardware. an intiic 0 interrupt request signal occurs when a local address has been set to the sva0 register and when t he address set to the sva0 register matches the slave address sent by the master device, or when an extension code has been received. 18.9 error detection in i 2 c bus mode, the status of the serial data bus (sda0) during data transmission is capt ured by the iic0 register of the transmitting device, so the iic 0 register data prior to transmission can be compared with the transmitted iic0 register data to enable detection of tr ansmission errors. a transmission error is judged as having occurred when the compared data values do not match. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 556 18.10 extension code (1) when the higher 4 bits of the receive address are eit her 0000 or 1111, the extension code flag (exc0) is set for extension code reception and an interrupt request signal (intiic0) is issued at the falling edge of the eighth clock. the local address stored in the sva0 register is not affected. (2) if 11110xx0 is set to the sva0 register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the int iic0 signal occurs at the fa lling edge of the eighth clock. ? higher 4 bits of data match: iics0.exc0 bit = 1 ? 7 bits of data match: iics0.coi0 bit = 1 (3) since the processing after the intiic0 signal occurs diffe rs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a sl ave is not desired after the extension code is received, set the iicc0.lrel0 bit to 1 and the cpu will enter the next communication wait state. table 18-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 557 18.11 arbitration when several master devices simultaneous ly output a start condition (when the iicc0.stt0 bit is set to 1 before the iics0.std0 bit is set to 1), communication among the ma ster devices is performed as the number of clocks is adjusted until the data differs. this ki nd of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (iic s0.ald0 bit) is set (1) via the timing by which the arbitration loss occurr ed, and the scl0 and sda0 lines are both set for high impedance, which releases the bus. the arbitration loss is detec ted based on the timing of the next interrupt request signal (i ntiic0) (the eighth or ninth clock, when a stop condition is detec ted, etc.) and the ald0 bit = 1 se tting that has been made by software. for details of interrupt request timing, refer to 18.6 i 2 c interrupt request signals (intiic0) . figure 18-11. arbitration timing example master 1 master 2 transfer lines scl0 sda0 scl0 sda0 scl0 sda0 master 1 loses arbitration hi-z hi-z chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 558 table 18-5. status during arbitration and interrupt request generation timing status during arbitration inte rrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data reception when restart condition is det ected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected duri ng data transfer when stop condition is output (when iicc0.spie0 bit = 1) note 2 when the sda0 pin is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when spie0 bit = 1) note 2 when the sda0 pin is at low level while attempting to output a stop condition when the scl0 pin is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iicc0.wtim0 bit = 1, an intiic0 signal o ccurs at the falling edge of the ninth clock. when the wtim0 bit = 0 and the extension code?s slave address is received, an intiic0 signal occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spie0 bit = 1 for master device operation. 18.12 wakeup function the i 2 c bus slave function is a function t hat generates an interrupt request signal (intiic0) when a local address or extension code has been received. this function makes processing more effi cient by preventing the unnecessary intiic0 signal from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wak eup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detect ed, the iicc0.spie0 bit is set regardl ess of the wakeup function, and this determines whether the intiic0 signal is enabled or disabled. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 559 18.13 communication reservation 18.13.1 when communication reservation func tion is enabled (iicf0.iicrsv0 bit = 0) to start master device communications when not current ly using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is re leased. there are two modes under which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack si gnal is not returned and the bus was released when the iicc0.lrel0 bit was set to 1). if the iicc0.stt0 bit is set (1) while the bus is not used, a start condition is automatic ally generated and wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detect ed), writing to the iic0 register causes the master?s address transfer to start. at this point, the iicc0.spie0 bit should be set (1). when the stt0 bit has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been re leased .............................................. a start condition is generated if the bus has not been released (standby mode) .............. comm unication reservation to detect which operation mode has been dete rmined for the stt0 bit, set the stt0 bi t (1), wait for the wait period, then check the iics0.msts0 bit. wait periods, which should be set via software, are listed in table 18-6. these wait periods can be set via the settings for the iiccl0.smc0, ii ccl0.cl01, and iiccl0.cl00 bits. table 18-6. wait periods smc0 cl01 cl00 wait period 0 0 0 26 clocks 0 0 1 46 clocks 0 1 0 92 clocks 0 1 1 37 clocks 1 0 0 1 0 1 16 clocks 1 1 0 32 clocks 1 1 1 13 clocks chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 560 the communication reservation timing is shown below. figure 18-12. communication reservation timing 2 13456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iic0 set spd0 and intiic0 stt0 =1 communication reservation set std0 output by master with bus access iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after the iics0.std0 bit is set to 1, a communication reservation can be made by setting the iicc0 .stt0 bit to 1 before a stop condition is detected. figure 18-13. timing for accep ting communication reservations scl0 sda0 std0 spd0 standby mode chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 561 the communication reservation flowchart is illustrated below. figure 18-14. communication reservation flowchart di stt0 = 1 define communication reservation wait cancel communication reservation no yes iic0 h ei msts0 = 0? (communication reservation) note (generate start condition) ; sets stt0 flag (communication reservation). ; gets wait period set by software (refer to table 18-6 ). ; confirmation of communication reservation ; clear user flag. ; iic0 write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation oper ation executes a write to the iic0 register when a stop condition interrupt request occurs. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 562 18.13.2 when communication reservation func tion is disabled (iicf0.iicrsv0 bit = 1) when the iicc0.stt0 bit is set when the bus is not us ed in a communication during bus communication, this request is rejected and a start condition is not generated. the followi ng two statuses are incl uded in the status where bus is not used. ? when arbitration results in nei ther master nor slave operation ? when an extension code is received and slave operation is disabled (ack signal is not returned and the bus was released when the iicc0.lrel0 bit was set to 1) to confirm whether the start conditi on was generated or request was rejected, check the iicf0.stcf0 flag. the time shown in table 18-7 is required until the stcf0 flag is set after setting the s tt0 bit = 1. therefore, secure the time by software. table 18-7. wait periods cl01 cl00 wait period 0 0 6 clocks 0 1 6 clocks 1 0 3 clocks 1 1 9 clocks chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 563 18.14 cautions (1) when iicf0.stcen0 bit = 0 immediately after i 2 c0 operation is enabled, the bus communica tion status (iicf0.iicbsy0 bit = 1) is recognized regardless of the actual bus status. to execute master comm unication in the status where a stop condition has not been detect ed, generate a stop condition and then releas e the bus before st arting the master communication. use the following sequence for generating a stop condition. <1> set the iiccl0 register. <2> set the iicc0.iice0 bit. <3> set the iicc0.spt0 bit. (2) when iicf0.stcen0 bit = 1 immediately after i 2 c0 operation is enabled, the bus released status (iicbsy0 bit = 0) is recognized regardless of the actual bus status. to issue t he first start condition (iicc0.stt0 bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. 18.15 communication operations 18.15.1 master operation 1 the following shows the flowchart for master communi cation when the communication reservation function is enabled (iicf0.iicrsv0 bit = 0) and the master operation is started after a stop condition is detected (iicf0.stcen0 bit = 0). chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 564 figure 18-15. master operation flowchart (1) iicc0 h iice0 = spie0 = wtim0 = 1 spt0 = 1 iiccl0 h select transfer clock stt0 = 1 start acke0 = 0 no no no no no no no no no yes yes yes yes yes yes yes intiic0 = 1? wtim0 = 0 acke0 = 1 intiic0 = 1? intiic0 = 1? trc0 = 1? ackd0 = 1? msts0 = 1? yes no intiic0 = 1? intiic0 = 1? ackd0 = 1? wrel0 = 1 start reception yes (stop condition detection) wait wait time is secured by software (refer to table 18-6 ) yes (start condition generation) communication reservation start iic0 write transfer stop condition detection, start condition generation by communication reservation generate stop condition (no slave with matching address) no (receive) address transfer completion yes (transmit) end start iic0 write transfer data processing transfer completed? generate stop condition spt0 = 1 (restart) end transfer completed? data processing chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 565 18.15.2 master operation 2 the following shows the flowchart for master communi cation when the communication reservation function is disabled (iicrsv0 bit = 1) and the ma ster operation is start ed without detecting a stop condition (stcen0 bit = 1). figure 18-16. master operation flowchart (2) no iiccl0 h iicf0 h iicc0 h iice0 = spie0 = wtim0 = 1 stt0 = 1 start no yes iicbsy0 = 0? no yes wtim0 = 0 acke0 = 1 wrel0 = 1 start reception acke0 = 0 spt0 = 1 generate stop condition no yes yes (transmit) intiic0 = 1? no yes yes intiic0 = 1? no yes intiic0 = 1? no yes ackd0 = 1? no yes no ackd0 = 1? trc0 = 1? stcf0 = 0? end transfer clock selection iicf0 register setting iicc0 register initial setting wait time is secured by software (refer to table 18-7 ) insert wait start iic0 write transfer stop master communication master communication is stopped because bus is occupied yes (address transfer completion) start iic0 write transfer generate stop condition (no slave with matching address) end data processing data processing reception completed? transfer completed? (restart) no (receive) chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 566 18.15.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiic0 interrupt (processing requiring a significant change of the operat ion status, such as st op condition detection during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiic0 interrupt servicing performs only status change processing and t hat the actual data communication is performed during the main processing. figure 18-17. software out line during slave operation i 2 c intiic0 setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main pr ocessing instead of the intiic0 signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progre ss (valid address detection stop condition detection, ack signal from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. th is is the same status as an intiic0 interrupt during normal data transfer. this flag is set in the interrupt servicing block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the interrupt servicing bl ock, so the first data is transmitted without clearance proce ssing (the address match is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of the iics0.trc0 bit. the following shows the operati on of the main processing bl ock during slave operation. start i 2 c0 and wait for the communication enabled status. when communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmissi on operation until the master device stops returning ack signal. when the master device stops returning ac k signal, transfer is complete. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 567 for reception, receive the required num ber of data and do not return ack signal for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart c ondition. this causes exit from communications. figure 18-18. slave operation flowchart (1) yes yes yes yes yes yes yes yes no no no no no no no no start communication mode? communication mode? communication mode? ready? ready? read data clear ready flag clear ready flag communication direction flag = 1? wtim0 = 1 wrel0 = 1 acke0 = 0 wrel0 = 1 acke0 = wtim0 = 1 ackd0 = 1? wrel0 = 1 clear communication mode flag data processing data processing transfer completed? iic0 data iicc0 xxh iice0 = 1 iiccl0 xxh iicf0 = xxh selection of transfer clock iicf0 register setting chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 568 the following shows an example of the pr ocessing of the slave device by an int iic0 interrupt (it is assumed that no extension codes are used here). during an intiic0 interr upt, the status is confirm ed and the following steps are executed. <1> when a stop condition is detect ed, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, the communica tion mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, w hen the ready flag is set, operation retu rns from the interrupt while the i 2 c0 bus remains in the wait status. remark <1> to <3> in the above correspond to <1> to <3> in figure 18-19 slave operation flowchart (2) . figure 18-19. slave operation flowchart (2) yes yes yes no no no intiic0 generated set ready flag interrupt servicing completed interrupt servicing completed interrupt servicing completed termination processing spd0 = 1? std0 = 1? coi0 = 1? lrel0 = 1 clear communication mode communication direction flag trc0 set communication mode flag clear ready flag <1> <2> <3> chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 569 18.16 timing of data communication when using i 2 c bus mode, the master device out puts an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the ma ster device transmits the iics0.trc0 bit that specifies the data transfer direction and then starts serial co mmunication with the slave device. the iic0 register?s shift operation is synchronized with the falling edge of the se rial clock (scl0 pin). the transmit data is transferred to the so latch and is output (msb first) via the sda0 pin. data input via the sda0 pin is captured by the iic0 register at the ri sing edge of the scl0 pin. the data communication timing is shown below. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 570 figure 18-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic0 address iic0 data iic0 ffh transmit start condition receive (when exc0 = 1) note note note to cancel slave wait, write ffh to iic0 or set wrel0. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 571 figure 18-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data iic0 ffh note iic0 ffh note iic0 data transmit receive note note note to cancel slave wait, write ffh to iic0 or set wrel0. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 572 figure 18-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie0 = 1) receive (when spie0 = 1) note to cancel slave wait, write ffh to iic0 or set wrel0. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 573 figure 18-21. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l h h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note note iic0 data start condition note to cancel master wait, writ e ffh to iic0 or set wrel0. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 574 figure 18-21. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note note to cancel master wait, writ e ffh to iic0 or set wrel0. chapter 18 i 2 c bus preliminary user?s manual u16895ej1v0ud 575 figure 18-21. example of sl ave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l h acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie0 = 1) n- ack (when spie0 = 1) note to cancel master wait, writ e ffh to iic0 or set wrel0. preliminary user?s manual u16895ej1v0ud 576 chapter 19 interrupt/except ion processing function 19.1 overview the v850es/kf1+ is provided with a dedica ted interrupt controller (intc) for interrupt servicing and realize an interrupt function that can service interrupt r equests from a total of 38 or 39 sources. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/kf1+ can process interrupt requests from t he on-chip peripheral hardware and external sources. moreover, exception processing can be star ted by the trap instruction (software exception) or by generation of an exception event (fetching of an illegal opcode) (exception trap). 19.1.1 features interrupt source v850es/kf1+ external 1 channel (nmi pin) non-maskable interrupt internal 2 channels (wdt1, wdt2) external 8 channels (all edge detection interrupts) wdt1 1 channel tmp 3 channels tm0 4 channels tmh 2 channels tm5 2 channels wt 2 channels brg 1 channel uart 6 channels csi0 2 channels csia 1 channel iic 1 channel note kr 1 channel ad 1 channel lvi 1 channel interrupt function maskable interrupt internal total 28 channels 16 channels (trap00h to trap0fh) software exception 16 channels (trap10h to trap1fh) exception function exception trap 2 channels (ilgop/dbg0) note only in the pd703308y, 70f3306y, 70f3308y table 19-1 lists the interrupt/exception sources. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 577 table 19-1. interrupt source list (1/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset internal reset input from wdt1, wdt2 wdt1 wdt2 0000h 00000000h u ndefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? ? intwdt1 wdt1 overflow (when non- maskable interrupt selected) wdt1 0020h 00000020h note 1 ? non- maskable interrupt ? intwdt2 wdt2 overflow (when non- maskable interrupt selected) wdt2 0030h 00000020h note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal opcode/dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm1 wdt1 overflow (when interval timer selected) wdt1 0080h 00000080h nextpc wdt1ic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin valid edge input pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge input pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge input pin 00f0h 000000f0h nextpc pic6 8 inttm000 tm00 and cr000 match tm00 0100h 00000100h nextpc tm0ic00 9 inttm001 tm00 and cr001 match tm00 0110h 00000110h nextpc tm0ic01 10 inttm010 tm01 and cr010 match tm01 0120h 00000120h nextpc tm0ic10 11 inttm011 tm01 and cr011 match tm01 0130h 00000130h nextpc tm0ic11 12 inttm50 tm50 and cr50 match tm50 0140h 00000140h nextpc tm5ic0 13 inttm51 tm51 and cr51 match tm51 0150h 00000150h nextpc tm5ic1 14 intcsi00 csi00 transfer completion csi00 0160h 00000160h nextpc csi0ic0 15 intcsi01 csi01 transfer completion csi01 0170h 00000170h nextpc csi0ic1 16 intsre0 uart0 reception error occurrence uart0 0180h 00000180h nextpc sreic0 17 intsr0 uart0 reception completion uart0 0190h 00000190h nextpc sric0 maskable interrupt 18 intst0 uart0 transmission completion uart0 01a0h 000001ah nextpc stic0 notes 1. for restoration in the case of intwdt1 and intwdt2, refer to 19.10 cautions . 2. n = 0 to fh chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 578 table 19-1. interrupt source list (2/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register 19 intsre1 uart1 reception error occurrence uart1 01b0h 000001b0h nextpc sreic1 20 intsr1 uart1 reception completion uart1 01c0h 000001c0h nextpc sric1 21 intst1 uart1 transmission completion uart1 01d0h 000001d0h nextpc stic1 22 inttmh0 tmh0 and cmp00/cmp01 match tmh0 01e0h 000001e0h nextpc tmhic0 23 inttmh1 tmh1 and cmp10/cmp11 match tmh1 01f0h 000001f0h nextpc tmhic1 24 intcsia0 csia0 transfer completion csia0 0200h 00000200h nextpc csiaic0 25 intiic0 note i 2 c0 transfer completion i 2 c0 0210h 00000210h nextpc iicic0 26 intad a/d conversion completion a/d 0220h 00000220h nextpc adic 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intwti watch timer interval wt 0240h 00000240h nextpc wtiic 29 intwt watch timer reference time wt 0250h 00000250h nextpc wtic 30 intbrg 8-bit counter of prescaler 3 and prscm match prescaler 3 0260h 00000260h nextpc brgic 45 intlvi low-voltage detection lvi 0380h 00000380h nextpc lviic 46 intp7 intp7 pin valid edge input pin 0390h 00000390h nextpc pic7 47 inttp0ov tmp0 overflow tmp 03a0h 000003a0h nextpc tpovic 48 inttp0cc0 tmp0 capture 0/ compare 0 match tmp 03b0h 000003b0h nextpc tpccic0 maskable interrupt 49 inttp0cc1 tmp0 capture 1/ compare 1 match tmp 03c0h 000003c0h nextpc tpccic1 note only in the pd703308y, 70f3306y, 70f3308y remarks 1. default priority: the priority order when two or more maskable interrupt requests with the same priority level are generated at the sa me time. the highest priority is 0. the priority of non-maskable interrupt request is as follows. intwdt2 > intwdt1 > nmi restored pc: the value of the program counter (pc) saved to eipc, fepc, or dbpc when interrupt/exception processing is started. the restored pc when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextpc (when an interrupt is acknowledged during the execution of an instruction, the execution of that in struction is stopped and is resumed following completion of interrupt servicing). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only w hen an interrupt occurs before stack pointer update) nextpc: the pc value at which processing is st arted following interrupt/exception processing. 2. the execution address of the illegal opcode when an illegal opcode exception occurs is calculated with (restored pc ? 4). chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 579 19.2 non-maskable interrupts non-maskable interrupt request signals are acknowledged unconditionally, even when interrupts are disabled (di state). non-maskable interrupts (nmi) are not subject to pr iority control and take precedence over all other interrupt request signals. the following three types of non-maskable interrupt request signals are available in the v850es/kf1+. ? nmi pin input (nmi) ? non-maskable interrupt request signal (intwdt1) due to overflow of watchdog timer 1 ? non-maskable interrupt request signal (intwdt2) due to overflow of watchdog timer 2 there are four choices for the valid edge of an nmi pin, namely: rising edge, falling edge, both edges, and no edge detection. the non-maskable interrupt request signal (intwdt1) due to overflow of watchdog timer 1 functions by setting the wdtm1.wdtm14 and wdtm1.wdtm13 bits to 10. the non-maskable interrupt request signal (intwdt2) due to overflow of watchdog timer 2 functions by setting the wdtm2.wdm21 and wdtm2.wdm20 bits to 01. when two or more non-maskable interrupts occur simultane ously, they are processed in a sequence determined by the following priority order (the interrupt requ est signals with low priority level are ignored). intwdt2 > intwdt1 > nmi if during nmi processing, an nmi, intwdt1, or intwdt2 r equest signal newly occurs, processing is performed as follows. (1) if an nmi request signal newly occurs during nmi processing the new nmi request signal is held pending regard less of the value of the psw.np bit. the nmi request signal held pending is acknowledged upon completi on of processing of the nm i currently being executed (following reti instruction execution). (2) if an intwdt1 request signal newly occurs during nmi processing if the np bit remains set (to 1) during nmi processing, the new intwdt1 request signal is held pending. the intwdt1 request signal held pending is acknowledged upon completion of processing of the nmi currently being executed (following re ti instruction execution). if the np bit is cleared (to 0) during nmi processing, a newly generated intwdt1 request signal is executed (nmi processing is interrupted). (3) if an intwdt2 request signal newly occurs during nmi processing a newly generated intwdt2 request signal is executed re gardless of the value of the np bit (nmi processing is interrupted). caution for non-maskable interrupt servicing from non-maskable interrupt re quest signals (intwdt1, intwdt2), refer to 19.10 cautions. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 580 figure 19-1. acknowledging non-maskab le interrupt request signals (1/2) (a) if two or more nmi request si gnals are simultan eously generated main routine system reset nmi, intwdt2 request (simultaneously generated) intwdt2 processing nmi and intwdt2 requests simultaneously generated main routine system reset nmi, intwdt1 request (simultaneously generated) intwdt1 processing nmi and intwdt1 requests simultaneously generated main routine system reset nmi, intwdt1, intwdt2 requests (simultaneously generated) intwdt2 processing nmi, intwdt1, and intwdt2 requests simultaneously generated main routine system reset intwdt1, intwdt2 request (simultaneously generated) intwdt2 processing intwdt1 and intwdt2 requests simultaneously generated chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 581 figure 19-1. acknowledging non-maskab le interrupt request signals (2/2) (b) if a new non-maskable interr upt request signal is generated during a non-maskable interrupt servicing non-maskable interrupt currently being serviced non-maskable interrupt request newly generated during non-maskable interrupt servicing nmi intwdt1 intwdt2 nmi generation of nmi request during nmi processing generation of intwdt1 request during nmi processing (np = 1 state prior to intwdt1 request is maintained) generation of intwdt1 request during nmi processing (set np = 0 before intwdt1 request) generation of intwdt1 request during nmi processing (set np = 0 after intwdt1 request) generation of intwdt2 request during nmi processing main routine nmi request nmi processing (held pending) nmi processing nmi request (hold pending) main routine system reset nmi request nmi request nmi processing intwdt1 processing (hold pending) main routine system reset nmi request nmi request nmi processing intwdt1 processing intwdt1 request np = 0 np = 0 main routine system reset intwdt2 request nmi processing intwdt2 processing generation of intwdt2 request during intwdt1 processing main routine system reset intwdt1 request intwdt1 processing intwdt2 processing intwdt2 request main routine system reset nmi processing intwdt1 processing intwdt1 (hold pending) request intwdt1 (invalid) request generation of intwdt1 request during intwdt1 processing main routine system reset intwdt1 processing generation of nmi request during intwdt1 processing intwdt1 intwdt2 main routine system reset intwdt1 request intwdt1 request intwdt1 processing nmi request (invalid) nmi request (invalid) generation of intwdt2 request during intwdt2 processing generation of intwdt1 request during intwdt2 processing main routine system reset intwdt2 processing main routine system reset intwdt2 processing generation of nmi request during intwdt2 processing main routine system reset intwdt2 request intwdt2 request intwdt2 processing intwdt1 (invalid) request intwdt2 (invalid) request intwdt1 request intwdt2 request chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 582 19.2.1 operation upon generation of a non-maskable interrupt request si gnal, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes the exception code (0010h, 0020h, 0030h ) to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. <5> loads the handler address (00000010h, 00000020h, 00000030h) of the non-maskable interrupt to the pc and transfers control. figure 19-2 shows the servicing flow for non-maskable interrupts. figure 19-2. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request held pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 handler address intc acknowledged cpu processing psw. np 1 0 chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 583 19.2.2 restore execution is restored from non-maskable inte rrupt servicing by the reti instruction. (1) in case of nmi restore from nmi processing is done with the reti instruction. when the reti instruction is executed , the cpu performs the following processing and transfers control to the address of the restored pc. (i) loads the values of the restored pc and psw from fepc and fepsw , respectively, because the psw.ep bit and the psw.np bit are 0 and 1, respectively. (ii) transfers control back to the load ed address of the restored pc and psw. figure 19-3 shows the processing fl ow of the reti instruction. figure 19-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep bit and the np bit are changed by the ldsr instruction dur ing non-maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and set the np bit back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. (2) in case of intwdt1 and intwdt2 signals for non-maskable interrupt servicing by the non-maskabl e interrupt request signals (intwdt1, intwdt2), refer to 19.10 cautions . chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 584 19.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt servicing is in progress. this flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt serving in progress np 0 1 nmi servicing status after reset: 00000020h chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 585 19.3 maskable interrupts maskable interrupt request signals can be masked by inte rrupt control registers. the v850es/kf1+ has 36 maskable interrupt sources (refer to 19.1.1 features ). if two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. in addition to the default pr iority, eight levels of interrupt priorities can be specified by using the interrupt control registers, allowing programmable priority control. when an interrupt request signal has been acknowledged, the interrupt disabled (di) status is set and the acknowledgment of other maskable inte rrupt request signals is disabled. when the ei instruction is executed in an interrupt servicing routine, the interr upt enabled (ei) status is set, which enables acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal currently in progress. note that only interrupt request signals with a higher priority have this capability; interrupt request signals with the same priority level cannot be nested. to use multiple interrupts, it is neces sary to save eipc and eipsw to memory or a register befor e executing the ei instruction, and restore eipc and eipsw to the original values by executing the di instruction before the reti instruction. when the wdtm1.wdtm14 bit is cleared to 0, the watchdog timer 1 overflow interrupt functions as a maskable interrupt (intwdtm1). 19.3.1 operation if a maskable interrupt request signal is generated, t he cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to t he lower halfword of ecr (eicc). <4> sets the psw.id bit to 1 and clears the psw.ep bit to 0. <5> loads the corresponding handler addr ess to the pc and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal that occurs while another interrupt is being serviced (when psw.np bit = 1 or id bit = 1) are held pending internally. when the interrupts are unmasked, or when the np bit = 0 and the id bit = 0 by using the reti and ldsr instructions, a new maskable interrupt servicing is started in accordance with th e priority of the pending maskable interrupt request signal. figure 19-4 shows the servicing flow for maskable interrupts. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 586 figure 19-4. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id ispr. corresponding- bit note pc intc acknowledged cpu processing interrupt mask released? priority higher than that of interrupt currently being serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt requests? highest default priority of interrupt requests with the same priority? restored pc psw exception code 0 1 1 handler address note for the ispr register, refer to 19.3.6 in-service prio rity register (ispr) . chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 587 19.3.2 restore execution is restored from maskable interrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. (1) loads the values of the restored pc and psw fr om eipc and eipsw because the psw.ep bit and the psw.np bit are both 0. (2) transfers control to the loaded address of the restored pc and psw. figure 19-5 shows the processing fl ow of the reti instruction. figure 19-5. reti instruction processing reti instruction original processing restored pc psw ispr. corresponding -bit note eipc eipsw 0 psw. ep 1 0 1 0 pc psw fepc fepsw psw. np note for the ispr register, refer to 19.3.6 in-service prio rity register (ispr) . caution when the ep bit and the np bit are ch anged by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and the np bit back to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 588 19.3.3 priorities of maskable interrupts intc provides a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority leve l control: control based on the default pr iority levels, and control based on the programmable priority levels specified by the interrupt priority level specificat ion bit (xxicn.xxprn bit). when two or more interrupts having the same priority level specifi ed by xxprn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request (default priority level) beforehand. for more information, refer to table 19-1 interrupt source list . programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request signal is acknowledged , the psw.id flag is automatically set (1). therefore, when multiple interrupts are to be used, clear (0) the id flag bef orehand (for example, by plac ing the ei instruction into the interrupt service program) to enable interrupts. remark xx: identifying name of eac h peripheral unit (refer to table 19-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 19-2 interrupt control registers (xxicn) ) chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 589 figure 19-6. example of interrupt nesting (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the re lative priority between two interrupt request signals. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 590 figure 19-6. example of interrupt nesting (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 591 figure 19-7. example of servicing simultan eously generated inte rrupt request signals main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b servicing of interrupt request c servicing of interrupt request a interrupt requests b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. notes 1. higher default priority 2. lower default priority chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 592 19.3.4 interrupt control register (xxlcn) an interrupt control register is assigned to each maska ble interrupt and sets the control conditions for each maskable interrupt request. the interrupt control registers can be read or written in 8-bit or 1-bit units. after reset, xxicn is set to 47h. caution be sure to read the xxicn. xxifn bit while interrupts are disabled (d i). if the xxifn bit is read while interrupts are enabled (e i), an incorrect value may be read if there is a conflict between acknowledgment of the interrupt and reading of the bit. xxifn interrupt request not generated interrupt request generated xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 enables interrupt servicing disables interrupt servicing (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest) specifies level 1 specifies level 2 specifies level 3 specifies level 4 specifies level 5 specifies level 6 specifies level 7 (lowest) xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff168h < > < > note automatically reset by hardware when interrupt request is acknowledged. remark xx: identifying name of eac h peripheral unit (refer to table 19-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 19-2 interrupt control registers (xxicn) ) following tables list the addresses and bits of the interrupt control registers. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 593 table 19-2. interrupt c ontrol registers (xxlcn) bits address register <7> <6> 5 4 3 2 1 0 fffff110h wdt1ic wdt1if wdt1mk 0 0 0 wdt1pr2 wdt1pr1 wdt1pr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h tm0ic00 tm0if00 tm0mk00 0 0 0 tm0pr002 tm0pr001 tm0pr000 fffff122h tm0ic01 tm0if01 tm0mk01 0 0 0 tm0pr012 tm0pr011 tm0pr010 fffff124h tm0ic10 tm0if10 tm0mk10 0 0 0 tm0pr102 tm0pr101 tm0pr100 fffff126h tm0ic11 tm0if11 tm0mk11 0 0 0 tm0pr112 tm0pr111 tm0pr110 fffff128h tm5ic0 tm5if0 tm5mk0 0 0 0 tm5pr02 tm5pr01 tm5pr00 fffff12ah tm5ic1 tm5if1 tm5mk1 0 0 0 tm5pr12 tm5pr11 tm5pr10 fffff12ch csi0ic0 csi0if0 csi0mk0 0 0 0 csi0pr02 csi0pr01 csi0pr00 fffff12eh csi0ic1 csi0if1 csi0mk1 0 0 0 csi0pr12 csi0pr11 csi0pr10 fffff130h sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff132h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff138h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff13ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff13ch tmhic0 tmhif0 tmhmk0 0 0 0 tmhpr02 tmhpr01 tmhpr00 fffff13eh tmhic1 tmhif1 tmhmk1 0 0 0 tmhpr12 tmhpr11 tmhpr10 fffff140h csiaic0 csiaif0 csiamk0 0 0 0 csiapr02 csiapr01 csiapr00 fffff142h iicic0 note iicif0 iicmk0 0 0 0 iicpr02 iicpr01 iicpr00 fffff144h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff146h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff148h wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff14ah wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff14ch brgic brgif brgmk 0 0 0 brgpr2 brgpr1 brgpr0 fffff170h lviic lviif lvimk 0 0 0 lvipr2 lvipr1 lvipr0 fffff172h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff174h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff176h tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccpr02 tp0ccpr01 tp0ccpr00 fffff178h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10 note only in the pd703308y, 70f3306y, 70f3308y chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 594 19.3.5 interrupt mask registers 0, 1, 3 (imr0, imr1, imr3) these registers set the interrupt mask status for maskable interrupts. the xxmkn bit of the imr0, imr1, and imr3 registers and the xxmkn bit of the xxlcn register are respectively linked. the imrm register can be read or wri tten in 16-bit units (m = 0, 1, 3). when the higher 8 bits of the imrk register are used as the imrkh regist er and the lower 8 bits of the imrk register as the imrkl register, they can be read or written in 8-bit or 1-bit units (k = 0, 1). caution in the device file, th e xxmkn bit of the xxicn register is de fined as a reserved word. therefore, if bit manipulation is performed using the name xxm kn, the xxicn register, not the imrm register, is rewritten (as a result, the imrm register is also rewritten). csi0mk1 pmk6 imr0 (imr0h note ) (imr0l) csi0mk0 pmk5 tm5mk1 pmk4 tm5mk0 pmk3 tm0mk11 pmk2 tm0mk10 pmk1 tm0mk01 pmk0 tm0mk00 wdt1mk after reset: ffffh r/w address: imr0 fffff100h, imr0l fffff100h, imr0h fffff101h after reset: ffffh r/w address: imr1 fffff102h, imr1l fffff102h, imr1h fffff103h 1 tmhmk1 imr1 (imr1h note ) (imr1l) brgmk tmhmk0 wtmk stmk1 wtimk srmk1 krmk sremk1 admk stmk0 iicmk0 srmk0 csiamk0 sremk0 xxmkn 0 1 enables interrupt servicing disables interrupt servicing 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 interrupt mask flag setting after reset: ffffh r/w address: imr3 fffff106h, imr3l fffff106h 1 1 imr3 (imr3l) 1 1 1 1 1 tp0ccmk1 1 tp0ccmk2 1 tp0ovfmk 1 pmk7 1 lvimk 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 note when reading from or writing to bits 8 to 15 of the imr0 and imr1 registers in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the imr0h and imr1h registers. caution set bit 15 of the imr1 register and bits 15 to 5 of the imr3 register to 1. the operation is not guaranteed if their value is changed. remark xx: identifying name of eac h peripheral unit (refer to table 19-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 19-2 interrupt control registers (xxicn) ) chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 595 19.3.6 in-service priority register (ispr) this register holds the priority level of the maskable in terrupt currently being ackno wledged. when the interrupt request signal is acknowledged, the bit of this register corres ponding to the priority level of that interrupt request signal is set (1) and remains set while the interrupt is being serviced. when the reti instruction is executed, t he bit among those that are set (1) in t he ispr register that corresponds to the interrupt request signal having the highest priority is aut omatically cleared (0) by hardw are. however, it is not cleared (0) when execution is returned from non-maskab le interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. after reset, ispr is cleared to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after th e bits of the register have been set to 1 by acknowledging the interrupt may be read. to accura tely read the value of the ispr register before an interrupt is acknowledge d, read the register while inte rrupts are disabled (di status). ispr7 interrupt request with priority n is not acknowledged interrupt request with priority n is being acknowledged isprn 0 1 priority of interrupt currently being acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah < > < > < > < > < > < > < > < > remark n = 0 to 7 (priority level) chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 596 19.3.7 id flag the interrupt disable flag (id) is allocated to the psw and controls the maskable inte rrupt?s operating state, and stores control information regarding enabling/disa bling reception of interrupt request signals. after reset, this flag is set to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled id 0 1 maskable interrupt servicing specification note after reset: 00000020h note interrupt disable flag (id) function id is set (1) by the di instruction and cleared (0) by the ei instruction. its value is also modified by the reti instruction or ld sr instruction when referencing the psw. non-maskable interrupt request signals and e xceptions are acknowledged regardless of this flag. when a maskable interrupt reques t signal is acknowledged, the id flag is automatically set (1) by hardware. an interrupt request signal generated during t he acknowledgment disabled period (id flag = 1) can be acknowledged when the xxicn.xxifn bit is set (1), and the id flag is cleared (0). chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 597 19.3.8 watchdog timer mode register 1 (wdtm1) this register is a special register that can be written to only in a s pecial sequence. to generate a maskable interrupt (intwdt1), clear the wdtm14 bit to 0. this register can be read or written in 8- bit or 1-bit units (for details, refer to chapter 12 watchdog timer functions ). run1 stop count operation clear counter and start count operation run1 0 1 watchdog timer operation mode selection note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (generate maskable interrupt intwdtm1 when overflow occurs) watchdog timer mode 1 note 3 (generate non-maskable interrupt intwdt1 when overflow occurs) watchdog timer mode 2 (start wdtres2 reset operation when overflow occurs) wdtm14 0 0 1 1 wdtm13 0 1 0 1 watchdog timer operation mode selection note 2 < > notes 1. once the run1 bit has been set (1), it cannot be cleared (0) by software. therefore, once counting starts, it cannot be stopped except by reset. 2. once the wdtm14 and wdtm13 bits have bee n set (1), they cannot be cleared (0) by software. reset is the only way to clear these bits. 3. for non-maskable interrupt servicing due to a non-maskable interrupt request signal (intwdt1), refer to 19.10 cautions . chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 598 19.4 external interrupt request i nput pins (nmi, intp0 to intp7) 19.4.1 noise elimination (1) noise elimination for nmi pin the nmi pin includes a noise eliminator that operates using analog delay. therefore, a signal input to the nmi pin is not detected as an edge unless it maintains its input level for a cert ain period. the edge is detected only after a certain period has elapsed. the nmi pin is used for releasing the stop mode. in the stop mode, noise elim ination using the system clock is not performed because the internal system clock is stopped. (2) noise elimination for intp0 to intp2 and intp4 to intp7 pins the intp0 to intp2 and intp4 to intp7 pins include a noise eliminator that operat es using analog delay. therefore, a signal input to each pin is not detected as an edge unless it ma intains its input level for a certain period. the edge is detected only after a certain period has elapsed. (3) noise elimination for intp3 pin the intp3 pin has a digital/analog noise eliminat or that can be selected by the nfc.nfen bit. the number of times the digital noise eliminator samp les signals can be selected by the nfc.nfsts bit from three or two. the sampling clock can be selected by the nfc.nfc2 to nfc.nfc0 bits from f xx /64, f xx /128, f xx /256, f xx /512, f xx /1024, and f xt . if the sampling clock is set to f xx /64, f xx /128, f xx /256, f xx /512, or f xx /1024, the sampling clock stops in the idle/stop mode. it c annot therefore be used to release the standby mode. to release the standby mode, select f xt as the sampling clock or select the analog noise eliminator. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 599 (a) digital noise eliminat ion control register (nfc) the nfc register controls elimination of noise on the intp3 pin. if f xt is used as the noise elimination clock, the external interrupt function of the in tp3 pin can be used even in the idle/stop mode. this register can be read or written in 8-bit or 1-bit units. after reset, nfc is cleared to 00h. nfen analog noise elimination digital noise elimination nfen 0 1 setting of intp3 pin noise elimination nfc nfsts 0 0 0 nfc2 nfc1 nfc0 number of samplings = 3 times number of samplings = 2 times nfsts 0 1 setting of number of samplings of digital noise elimination after reset: 00h r/w address: fffff318h f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 f xt nfc2 0 0 0 0 1 1 nfc1 0 0 1 1 0 0 nfc0 0 1 0 1 0 1 selection of sampling clock setting prohibited other than above remark f xx : main clock frequency f xt : subclock frequency chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 600 chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 601 (1) external interrupt rising and falling e dge specification registers 0 (intr0, intf0) these are 8-bit registers t hat specify detection of the rising and fa lling edges of the nmi and intp0 to intp3 pins. these registers can be read or wri tten in 8-bit or 1-bit units. after reset, these registers are cleared to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf0n and intr0n bits = 00. 0 intr0 intr06 intr05 intr04 intr03 intr02 intp2 intp1 intp0 nmi 00 after reset: 00h r/w address: intr0 fffffc20h, intf0 fffffc00h intp2 intp1 intp0 nmi intp3 intp3 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 remark for specification of the valid edge, refer to table 19-3 . table 19-3. nmi and intp0 to in tp3 pins valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 602 (2) external interrupt rising and falling e dge specification registers 3 (intr3, intf3) these are 8-bit registers that s pecify detection of the rising and fall ing edges of the intp7 pin. these registers can be read or wri tten in 8-bit or 1-bit units. after reset, these registers are cleared to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf31 and intr31 bits = 00. 0 intr3 0 0 0 0 0 intr31 0 after reset: 00h r/w address: intr3 fffffc26h, intf3 fffffc06h intp7 intp7 0 intf3 0 0 0 0 0 intf31 0 remark for specification of the valid edge, refer to table 19-4 . table 19-4. intp7 pin valid edge specification intf31 intr31 valid edge specification 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 603 (3) external interrupt rising and falling edge specification registers 9h (intr9h, intf9h) these are 8-bit registers that s pecify detection of the rising edge of the intp4 to intp6 pins. these registers can be read or wri tten in 8-bit or 1-bit units. after reset, these registers are cleared to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf9n and intr9n bits = 00. intr915 intr9h intr914 intr913 0 0 0 0 0 after reset: 00h r/w address: intr9h fffffc33h, intf9h fffffc13h intp5 intp4 intp6 intp5 intp4 intp6 intf915 intf9h intf914 intf913 0 0 0 0 0 remark for specification of the valid edge, refer to table 19-5 . table 19-5. intp4 to intp6 pins valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 13 to 15: control of intp4 to intp6 pins chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 604 19.5 software exceptions a software exception is generated when the cpu executes the trap instruction. software exceptions can always be acknowledged. 19.5.1 operation if a software exception occurs, the cpu performs the fo llowing processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1. <5> loads the handler address (00000040h or 00000050h) for the software exception routine to the pc and transfers control. figure 19-8 shows the software exception processing flow. figure 19-8. software exception processing trap instruction note eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note trap instruction format: trap vector (however, vector = 00h to 1fh) the handler address is determined by the operand (vector) of the trap instructio n. if the vector is 00h to 1fh, the handler address is 00000040h, and if the vector is 10h to 1fh, the handler address is 00000050h. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 605 19.5.2 restore execution is restored from software exceptio n processing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. figure 19-9 shows the processing fl ow of the reti instruction. figure 19-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep bit and the np bit are ch anged by the ldsr instruction during software exception processing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to set th e ep bit back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 606 19.5.3 ep flag the ep flag is a status flag that indica tes that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress exception processing in progress ep 0 1 exception processing status after reset: 00000020h chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 607 19.6 exception trap the exception trap is an interrupt that is requested when t he illegal execution of an instruction takes place. in the v850es/kf1+, an illegal opcode trap (ilgop) is considered as an exception trap. 19.6.1 illegal opcode an illegal opcode is defined as an instruction with instru ction opcode (bits 10 to 5) = 111111b, sub-opcode (bits 26 to 23) = 0111b to 1111b, and sub-opcode (bit 16) = 0b. when such an instruction is ex ecuted, an exception trap is generated. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 x: don?t care caution it is recommended not to use illegal opcode because instructi ons may newly be assigned in the future. (1) operation upon generation of an exception trap, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits. <4> loads the handler address (00000060h) for the except ion trap routine to the pc and transfers control. figure 19-10 shows the exception trap processing flow. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 608 figure 19-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore execution is restored from exception trap processing by the dbret instruction. when the dbret instruction is executed, the cpu performs the fo llowing processing and transfers cont rol to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. figure 19-11 shows the processing flow for re store from exception trap processing. figure 19-11. processing flow fo r restore from exception trap dbret instruction pc psw dbpc dbpsw jump to restored pc address chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 609 19.6.2 debug trap a debug trap is an exception that occurs upon execution of the dbtrap inst ruction and that can be acknowledged at all times. when a debug trap occurs, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) for the debug trap routine to the pc and transfers control. figure 19-12 shows the debug trap processing flow. figure 19-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 610 (2) restore execution is restored from debug trap pr ocessing by the dbret instruction. when the dbret instruction is executed, the cpu performs the following processing and tr ansfers control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. figure 19-13 shows the processing flow fo r restore from debug trap processing. figure 19-13. processing flow for restore from debug trap dbret instruction pc psw dbpc dbpsw jump to restored pc address chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 611 19.7 multiple interru pt servicing control multiple interrupt servicing control is a function that st ops an interrupt service routine currently in progress if a higher priority interrupt request signal is generated, and processes the acknowledgm ent operation of the higher priority interrupt request signal. if an interrupt request signal with a lower or equal priority is generated and a service routi ne is currently in progress, the later interrupt request signal will be held pending. multiple interrupt servicing control is performed when inte rrupts are enabled (psw.id bit = 0). even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (id bit = 0). if a maskable interrupt or software exception is generated in a maskable interrupt or software exception service program, eipc and eipsw must be saved. the following example illustrates the procedure. (1) to acknowledge maskable interrupt re quest signals in service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgment) ? ? acknowledges maskable interrupt ? ? ? di instruction (disables interrupt acknowledgment) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 612 (2) to generate exception in service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ? trap instruction acknowledges exceptions su ch as trap instruction. ? ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction priorities 0 to 7 (0 is the highest) can be set for each maskable interrupt request in multiple interrupt servicing control by software. to set a priority level, wr ite values to the xxicn.xxp rn0 to xxicn.xxprn2 bits corresponding to each maskable interrupt request. after reset, interrupt requests are masked by the xxicn.xxmkn bit, and the priority is set to level 7 by the xxprn0 to xxprn2 bits. priorities of maskable interrupts are as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been suspend ed as a result of multiple interrupt servicing control is resumed after the interrupt servicing of the higher priority has been completed and the reti inst ruction has been executed. a pending interrupt request signal is acknowledged a fter the current interrupt servicing has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing rout ine (in the time until the reti instruction is executed), maskable interrupts are not acknowledged and held pending. chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 613 19.8 interrupt response time except in the following cases, the cpu interrupt response ti me is a minimum of 4 clocks. if inputting consecutive interrupt request signals, at least 4 clocks must be placed between each interrupt request signal. ? idle/stop mode ? external bus access ? consecutive interrupt request non- sample instruction (refer to 19.9 periods in which interrupts are not acknowledged by cpu ) ? access to interrupt control register ? access to peripheral i/o register figure 19-14. pipeline operati on during interrupt request si gnal acknowledgment (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clocks (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clocks remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt response time (internal system clock) internal interrupt external interrupt condition min. 4 4 + analog delay max. 6 6 + analog delay the following cases are excluded. ? idle/stop mode ? external bus access ? consecutive interrupt request non-sample instruction ? access to interrupt control register ? access to peripheral i/o register chapter 19 interrupt/exception processing function preliminary user?s manual u16895ej1v0ud 614 19.9 periods in which interrupts are not acknowledged by cpu interrupts are acknowledged by the cpu while an instru ction is being executed. however, no interrupt is acknowledged between an interrupt request non-sample instru ction and the next instru ction (interrupts are held pending). the following instructions are interrupt request non-sample instructions. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instructions (vs. psw) ? store instruction for the prcmd register ? store instruction and set1, not1, and clr1 instructions for the following registers ? interrupt-related registers: interrupt control register (xxlcn), interrupt mask registers 0, 1, 3 (imr0, imr1, imr3) ? power save control register (psc) 19.10 cautions design the system so that restoring by the reti instructi on is as follows after a non-maskable interrupt triggered by a non-maskable interrupt request signal (intwdt1/intwdt2) is serviced. figure 19-15. restoring by reti instruction generation of intwdt1/intwdt2 intwdt1/intwdt2 servicing routine software reset processing routine fepc software reset processing address fepsw value so that np bit = 1, ep bit = 1 reti ten reti instructions (fepc and fepsw must be set) psw initial set value of psw initialization processing preliminary user?s manual u16895ej1v0ud 615 chapter 20 key interrupt function 20.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the krm register. caution if any of the kr0 to kr7 pins is at low l evel, the intkr signal is not generated even if a falling edge is input to another pin. table 20-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 20-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 chapter 20 key interrupt function preliminary user?s manual u16895ej1v0ud 616 20.2 register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or writt en in 8-bit or 1-bit units. after reset, krm is cleared to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 key return mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution if the krm register is changed, an interrupt request signal (intkr) may be generated. to prevent this, change th e krm register after disabling interrupts (di), and then enable interrupts (ei) a fter clearing the interrupt request flag (kric.krif bit) to 0. remark for the alternate-function pin settings, refer to table 4-14 settings when port pins are used for alternate functions . preliminary user?s manual u16895ej1v0ud 617 chapter 21 standby function 21.1 overview the power consumption of the system can be effectively reduced by using t he standby modes in combination and selecting the appropriate mode for the application. the available standby modes are listed in table 21-1. table 21-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the operations of the internal circuits except the oscillator note 1 stop mode mode to stop all the operations of the internal circuits except the subclock oscillator note 2 subclock operation mode mode to use the subclock as the internal system clock sub-idle mode mode to stop all the operations of the internal circuits, except the oscillator, in the subclock operation mode ring clock operation mode note 3 mode in which the internal system clock (f clk ) operates on the ring clock by using the clock monitor function ring halt mode note 3 mode in which only the operating clock of the cpu (f cpu ) is stopped in the ring clock operation mode notes 1. the pll does not stop. to realize low power consum ption, stop the pll and then shift to the idle mode. 2. change to the clock-through mode, stop the pll, t hen shift to the stop mode. for details, refer to chapter 6 clock generation function . 3. for details of the ring clock operat ion mode and ring halt mode, refer to chapter 23 clock monitor . chapter 21 standby function preliminary user?s manual u16895ej1v0ud 618 figure 21-1. status transition (1/2) normal operation mode (main clock operation) wait for stabilization of oscillation wait for stabilization of oscillation setting of halt mode specification of subclock operation mode specification of normal operation mode specification of idle mode interrupt request note 8 specification of halt mode interrupt request note 10 setting of stop mode idle mode ring halt mode halt mode sub-idle mode stop mode reset note 3 interrupt request note 2 setting of idle mode interrupt request note 4 interrupt request note 6 subclock operation mode (subclock operation) ring clock operation mode (ring-osc operation) reset note 1 reset note 1 reset note 7 reset note 7 note 5 note 5 note 5 note 5 wait for stabilization of oscillation wait for stabilization of oscillation wait for stabilization of oscillation clmres note 9 reset note 3 reset note 3 note 5 note 5 wait for stabilization of oscillation wait for stabilization of oscillation note 5 chapter 21 standby function preliminary user?s manual u16895ej1v0ud 619 figure 21-1. status transition (2/2) notes 1. reset pin input, wdtres2, pocr es, lvires, or clmres signal. in the case of the wdtres1 signal, the osci llation stabilization time is not secured. 2. non-maskable interrupt request signal or unmasked maskable interrupt request signal. 3. reset pin input, wdtres2, pocres, or lvires signal. 4. non-maskable interrupt request signal (nmi pin input, intwdt2 signal) or unmasked internal interrupt request signal from peripheral functions operable in stop mode. 5. the main clock (f x ) starts oscillating. after the oscillatio n stabilization time, the normal operation mode is set. if watchdog timer 2 overflows while the oscillati on stabilization time is being secured because of an abnormality (stoppage) of the main clock oscillation (f x ), the ring clock operation mode is set. 6. non-maskable interrupt request signal (nmi pin input, intwdt2 signal) or unmasked internal interrupt request signal from peripheral functions operable in idle mode. 7. reset pin input, wdtres2, pocres, or lvires signal. while the main clock (f x ) is oscillating, the standby mode can be released by the clmres signal (refer to note 9 ). 8. non-maskable interrupt request signal (nmi pin input, intwdt2 signal) or unmasked internal interrupt request signal from peripheral functions operable in sub-idle mode. 9. if the main clock oscillation (f x ) is abnormal (stops), watchdog time r 1 does not count the oscillation stabilization time. when watchdog timer 2 counts the ring clock and overflows, the ring clock operation mode is set. 10. non-maskable interrupt request signal (nmi pin input, intwdt2 signal) or unmasked internal interrupt request signal from peripheral functions operable in ring halt mode. remarks 1. wdtres1 signal: reset signal by watchdog timer 1 overflow 2. wdtres2 signal: reset signal by watchdog timer 2 overflow 3. pocres signal: reset signal by power-on-clear circuit 4. lvires signal: reset signal by low-voltage detector 5. clmres signal: reset si gnal by clock monitor chapter 21 standby function preliminary user?s manual u16895ej1v0ud 620 21.2 registers (1) power save control register (psc) this is an 8-bit register that controls the standby function. the stp bit of this register is used to specify the standby mode. the psc register is a special register that can be written to only in a special sequence (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. after reset, psc is cleared to 00h. nmi2m psc 0 nmi0m intm 0 0 stp 0 releasing standby mode note by intwdt2 signal enabled releasing standby mode note by intwdt2 signal disabled nmi2m 0 1 control of releasing standby mode note by intwdt2 signal releasing standby mode note by nmi pin input enabled releasing standby mode note by nmi pin input disabled nmi0m 0 1 control of releasing standby mode note by nmi pin input releasing standby mode note by maskable interrupt request signals enabled releasing standby mode note by maskable interrupt request signals disabled intm 0 1 control of releasing standby mode note by maskable interrupt request signals normal mode standby mode note stp 0 1 standby mode note setting after reset: 00h r/w address: fffff1feh < > < > < > < > note in this case, standby mode means the idle/s top mode; it does not in clude the halt mode. cautions 1. if the nmi2m, nmi0m, and intm bits, and the stp bit are set to 1 at the same time, the setting of nmi2m, nmi0m, and intm bits b ecomes invalid. if th ere is an unmasked interrupt request signal being held pending when the idle/stop mode is set, set the bit corresponding to the interrupt request signal (n mi2m, nmi0m, or intm) to 1, and then set the stp bit to 1. 2. when the idle/stop mode is set, set the psmr.psm bit and then set the stp bit to 1. chapter 21 standby function preliminary user?s manual u16895ej1v0ud 621 (2) power save mode register (psmr) this is an 8-bit register that contro ls the operation status in the power save mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. after reset, psmr is cleared to 00h. xtstp subclock oscillator used subclock oscillator not used xtstp 0 1 specification of subclock oscillator use psmr 0 0 0 0 0 0 psm idle mode stop mode psm 0 1 specification of operation in standby mode after reset: 00h r/w address: fffff820h < > cautions 1. be sure to clear the xtstp bi t to 0 during subclock resonator connection. 2. be sure to clear bits 1 to 6 of the psmr register to 0. 3. the psm bit is valid only when the psc.stp bit is 1. chapter 21 standby function preliminary user?s manual u16895ej1v0ud 622 (3) oscillation stabilization time selection register (osts) the wait time until the oscill ation stabilizes after the stop mode is releas ed is controlled by the osts register. the osts register can be read or written in 8-bit units. after reset, osts is set to 01h. 0 osts 0 0 0 0 osts2 osts1 osts0 2 13 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 19 /f x 2 20 /f x 2 21 /f x osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 5 mhz 10 mhz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 4 mhz 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms f x after reset: note r/w address: fffff6c0h note this register is set to 00h or 01h, dependin g on the setting of the mask option/option byte. for details, refer to chapter 28 mask option/option byte . cautions 1. the wait time following release of the stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the stop mode, regardless of whether the stop mode is released by re set or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to 0. 3. the oscillation stabilization time is also inserted during external clock input. remark f x : main clock oscillation frequency chapter 21 standby function preliminary user?s manual u16895ej1v0ud 623 21.3 halt mode 21.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock s upply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 21-3 shows the operation status in the halt mode. the average power consumption of the system can be reduc ed by using the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed with an unmasked interrupt request signal held pending, the system shifts to the halt mode, but the halt mode is immediately released by the pending interrupt request signal. 21.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt1, intwdt2 signal), an unmasked maskable interrupt request signal, and reset signal (reset pin input, wdtres1, wdtres2, pocres, lvires, clmres signal). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interr upt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the halt mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the halt mode is released and that interrupt request signal is acknowledged. table 21-2. operation after releasing halt mode by interr upt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing halt mode by reset the same operation as the normal reset operation is performed. chapter 21 standby function preliminary user?s manual u16895ej1v0ud 624 table 21-3. operation status in halt mode when cpu is operating with main clock setting of halt mode item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled ring-osc (f r ) operable interrupt controller operable 16-bit timer (tmp0) operable 16-bit timers (tm00, tm01) operable 8-bit timers (tm50, tm51) operable timer h (tmh0, tmh1) operable watch timer operable when main clock is selected as count clock operable watchdog timer 1 operable watchdog timer 2 operable when ring-osc (f r ) is selected as count clock operable csi00, csi01 operable csia0 operable i 2 c0 note operable serial interface uart0, uart1 operable key interrupt function operable a/d converter operable real-time output operable clock monitor (clm) operable power-on-clear (poc) operable low-voltage detection (lvi) operable regulator operable port function retains status before halt mode was set. external bus interface refer to 2.2 pin status . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. note only in the pd703308y, 70f3306y, 70f3308y chapter 21 standby function preliminary user?s manual u16895ej1v0ud 625 21.4 idle mode 21.4.1 setting and operation status the idle mode is set by clearing the psmr.psm bit to 0 and setting the psc.stp bit to 1 in the normal operation mode. in the idle mode, the clock oscillator continues operati on but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on -chip peripheral functions that can operate with the subclo ck, ring-osc clock, or an external clock continue operating. table 21-5 shows the operation status in the idle mode. the idle mode can reduce the power consumption more than the halt m ode because it stops the operation of the on-chip peripheral functions. the main clock oscill ator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the idle mode. chapter 21 standby function preliminary user?s manual u16895ej1v0ud 626 21.4.2 releasing idle mode the idle mode is released by a non-maskable interr upt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the idle mode, or reset (e xcept wdtres1 signal). after the idle mode has been released, th e normal operation mode is restored. (1) releasing idle mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the idle mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interr upt request. if the idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the idle mode is released and that interrupt request signal is acknowledged. table 21-4. operation after releasing id le mode by interr upt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is di sabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle mode is not released. (2) releasing idle mode by reset the same operation as the normal reset operation is performed. chapter 21 standby function preliminary user?s manual u16895ej1v0ud 627 table 21-5. operation status in idle mode when cpu is operating with main clock setting of idle mode item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation enabled subclock oscillator ? ? ? chapter 21 standby function preliminary user?s manual u16895ej1v0ud 628 21.5 stop mode 21.5.1 setting and operation status the stop mode is set when the psmr.psm bit is set to 1 and the psc.stp bit is set to 1 in the normal operation mode. in the stop mode, the subclock oscillat or continues operating but the main cl ock oscillator stops. clock supply to the cpu and the on-chip peri pheral functions is stopped. as a result, program execution is st opped, and the contents of the inter nal ram before the stop mode was set are retained. the cpu and other on-ch ip peripheral functions stop operating. however, the on-chip peripheral functions that can operate wit h the subclock oscillator, ring-osc clock, or an external clock continue operating. table 21-7 shows the operation status in the stop mode. because the stop mode stops operation of the main clock oscillator, it reduc es the power consumption to a level lower than the idle mode. if the subclock oscillator, rin g-osc clock, and external clock are not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the stop mode. chapter 21 standby function preliminary user?s manual u16895ej1v0ud 629 21.5.2 releasing stop mode the stop mode is released by a non-maskable interr upt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the stop mode, or reset (except wdtres1 signal). after the stop mode has been released, the normal operat ion mode is restored after the oscillation stabilization time has been secured. (1) releasing stop mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interr upt request. if the stop mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the stop mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the stop mode is released and that interrupt request signal is acknowledged. table 21-6. operation after releasing st op mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is di sabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and stop mode is not released. (2) releasing stop mode by reset the same operation as the normal reset operation is performed. chapter 21 standby function preliminary user?s manual u16895ej1v0ud 630 table 21-7. operation status in stop mode when cpu is operating with main clock setting of stop mode item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation stops subclock oscillator ? chapter 21 standby function preliminary user?s manual u16895ej1v0ud 631 21.5.3 securing oscillation stabilization time when stop mode is released when the stop mode is released, only the oscillation stabilization time set by the osts register elapses. if the stop mode has been released by reset, howeve r, the reset value of the osts register note elapses. the operation performed when the stop mode is releas ed by an interrupt request signal is shown below. figure 21-2. oscillation stabilization time oscillated waveform main clock oscillator stops oscillation stabilization time count main clock stop mode status interrupt request note the reset value of the osts register differs dependi ng on the setting of the ma sk option/option byte. for details, refer to chapter 28 mask option/option byte . caution for details of the osts register, refer to 21.2 (3) oscillation stabilization time selection register (osts). chapter 21 standby function preliminary user?s manual u16895ej1v0ud 632 21.6 subclock operation mode 21.6.1 setting and operation status the subclock operation mode is set when the pcc.ck3 bit is set to 1 in the normal operation mode. when the subclock operation mode is set, t he internal system clock is changed from the main clock to the subclock. when the pcc.mck bit is set to 1, the op eration of the main clock oscillator is stopped. as a result, the system operates only with the subclock. table 21-8 shows the operation stat us in subclock operation mode. in the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. in addition, the power consumption can be further reduced to the level of the stop mode by st opping the operation of t he main clock oscillator. cautions 1. when manipulating the ck3 bit, do no t change the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to ma nipulate the bit is recommended). for details, refer to 6.3 (1) processor cl ock control register (pcc). 2. if the following conditions are not satisfied, change the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. main clock (f xx ) > subclock (f xt : 32.768 khz) 4 21.6.2 releasing subclock operation mode the subclock operation mode is released when the ck3 bit is cleared to 0 or by reset. if the main clock is stopped (mck bit = 1), set the mck bit to 1, secu re the oscillation stabilization time of the main clock by software, and clear the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for deta ils, refer to 6.3 (1) processor clock control register (pcc). chapter 21 standby function preliminary user?s manual u16895ej1v0ud 633 table 21-8. operation status in subclock operation mode operation status setting of subclock operation mode item when main clock is oscillati ng when main clock is stopped cpu operable rom correction operable subclock oscillator oscillation enabled ring-osc (f r ) operable interrupt controller operable 16-bit timer (tmp0) operable stops operation 16-bit timers (tm00, tm01) o perable tm00: stops operation tm01: operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) operable ? ? chapter 21 standby function preliminary user?s manual u16895ej1v0ud 634 21.7 sub-idle mode 21.7.1 setting and operation status the sub-idle mode is set when the psmr.psm bit is cleared to 0 and the psc.stp bit is set to 1 in the subclock operation mode. in this mode, the clock oscillator continues operation bu t clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is st opped and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and t he other on-chip peripheral functions are st opped. however, the on-chip peripheral functions that can operat e with the subclock, ring-osc clock, or an external clock continue operating. table 21-10 shows the operation status in the sub-idle mode. because the sub-idle mode stops oper ation of the cpu and other on-chip per ipheral functions, it can reduce the power consumption more than the subc lock operation mode. if the sub-idle mode is set after the main clock has been stopped, the power consumption can be reduced to a level as lo w as that in the stop mode. 21.7.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable inte rrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp 7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the s ub-idle mode, or reset (except wdtres1 signal). when the sub-idle mode is released by an interrupt requ est signal, the subclock operation mode is set. if it is released by reset, the normal operation mode is restored. (1) releasing sub-idle m ode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of t he interrupt request. if the sub-idle mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the sub-idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-idle mode is released and that interrupt request signal is acknowledged. table 21-9. operation after releasing sub- idle mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is di sabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and sub-idle mode is not released. (2) releasing sub-id le mode by reset the same operation as the normal reset operation is performed. chapter 21 standby function preliminary user?s manual u16895ej1v0ud 635 table 21-10. operation status in sub-idle mode operation status setting of sub-idle mode item when main clock is oscillati ng when main clock is stopped cpu stops operation rom correction stops operation subclock oscillator oscillation enabled ring-osc (f r ) operable interrupt controller stops operation 16-bit timer (tmp0) stops operation 16-bit timers (tm00, tm01) tm00: stops operation tm01: operable when intwt is selected as count clock tm00: stops operation tm01: operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) ? ? ? ? preliminary user?s manual u16895ej1v0ud 636 chapter 22 reset function 22.1 overview the following reset functions are available. ? reset by reset pin input ? reset by watchdog timer 1 overflow (wdtres1) ? reset by watchdog timer 2 overflow (wdtres2) ? system reset by low-volta ge detector (lvi) (lvires) ? system reset by clock monitor (clm) (clmres) ? system reset by power-on-clear (poc) (pocres) ? analog/digital + analog noise eliminator of reset pin selectable ? reset output function (p00/toh0 pin) 22.2 configuration figure 22-1. reset block diagram reset noise eliminator reset controller count clock watchdog timer 1 wdtres1 reset signal to cpu reset signal to cg reset signal to other peripheral macros low-voltage detector lvires clock monitor clmres power-on-clear pocres count clock f x ring-osc v dd v dd watchdog timer 2 wdtres2 chapter 22 reset function preliminary user?s manual u16895ej1v0ud 637 22.3 register to check reset source (1) reset source flag register (resf) the resf register is a special regist er that can be written only by a co mbination of specific sequences (refer to 3.4.7 special registers ). the resf register indicates the source from which a reset signal is generated. this register can be read or written in 8-bit or 1-bit un its (however, only ?0? can be written to this register). reset pin input or reset by the poc circuit (pocres) clear s this register to 00h. t he default value differs if reset is effected from a source other than the reset pin. wdt1rf wdt2rf 0 1 not generated generated resf 0 0 wdt2rf 0 0 clmrf lvirf after reset: 00h note r/w address: fffff888h reset signal from watchdog timer 2 (wdtres2) wdt1rf 0 1 not generated generated reset signal from watchdog timer 1 (wdtres1) lvirf 0 1 not generated generated reset signal from low-voltage detector (lvires) clmrf 0 1 not generated generated reset signal from clock monitor (clmres) note this register is cleared to 00h when a reset is executed via the reset pin or poc circuit. when a reset is executed by the wdtres1 signal, wdtres2 signal, low-voltage detector (lvi), or clock monitor (clm), the reset fl ags of this register (wdt1rf, wdt2rf, clmrf, and lvirf bits) are set (with the other sources retained). caution only ?0? can be written to each bit of this register. if writ ing ?0? conflicts wit h setting the flag (occurrence of reset), setting the flag takes precedence. chapter 22 reset function preliminary user?s manual u16895ej1v0ud 638 22.4 reset sources the following six reset sources are available. ? reset by reset pin input ? reset by watchdog timer 1 overflow (wdtres1) ? reset by watchdog timer 2 overflow (wdtres2) ? system reset by low-volt age detector (lvi) (lvires) ? system reset by clock monitor (clm) (clmres) ? system reset by power-on-clear (poc) (pocres) 22.4.1 reset operation via reset pin when a low level is input to the reset pin, the syst em is reset, and each hardware unit is initialized. the reset pin has a noise eliminator that can eliminate analog noise or digital + analog noise, depending on the setting of the rnzc register. while a low level is being input to the reset pin, the ma in clock oscillator stops. t herefore, the overall power consumption of the system can be reduced. when the level of the reset pin is changed from low to high, the reset status is released. if the reset status is released by reset pin input, the osci llation stabilization time elapses and then the cpu starts program execution (for the oscillation stabilization time, refer to 21.2 (3) oscillation stabilization time selection register (osts) and chapter 28 mask option/option byte ). table 22-1. hardware status on reset pin input item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues ring-osc (f r ) oscillation stops oscillation starts peripheral clock (f xx to f xx /1024) operation stops operation starts after securing oscillation stabilization time internal system clock (f clk ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) watchdog timer 1 clock (f xw ) operation stops operation starts cpu initialized program execution starts after securing oscillation stabilization time internal ram undefined if power-on reset or writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value imm ediately before reset input is retained. i/o lines (p00) low-level output i/o lines (ports other than p00) high impedance on-chip peripheral i/o registers initialized to specified status watchdog timer 2 operation st ops operation starts (f r ) other on-chip peripheral fu nctions operation stops operation can be started after securing oscillation stabilization time chapter 22 reset function preliminary user?s manual u16895ej1v0ud 639 figure 22-2. hardware status on reset pin input oscillation stabilization time count initialized to f xx /8 operation overflow of oscillation stabilization time counter internal system reset signal (active low) analog delay (eliminated as noise) analog delay eliminated as noise reset f x f clk detected as reset figure 22-3. operation on power application oscillation stabilization time count initialized to f xx /8 operation overflow of oscillation stabilization time counter internal system reset signal (active low) reset f x ev dd f clk v dd analog delay chapter 22 reset function preliminary user?s manual u16895ej1v0ud 640 (1) elimination of digital noise on reset pin for the reset pin of the v850es/ kf1+, an analog/digital + analog noise eliminator can be selected. the digital noise eliminator is sele cted when the rnzc.rnzsel bit = 1. the digital noise is sampled using the main clock (f x ), and the number of samplings can be sele cted from 10 or 20 by the rnzc.smpsel bit. (a) reset noise elimination control register (rnzc) the rnzc register can be read or written in 8-bit units. after reset, rnzc is cleared to 00h. 0 smpsel 0 1 20 times 10 times rnzc 0 0 0 0 0 smpsel rnzsel note after reset : 00h r/w address: fffff860h selection of number of samplings rnzsel note 0 1 analog noise elimination only digital + analog noise elimination selection of noise eliminator of reset pin note if the sampling clock is stopped, only the analog noi se is eliminated automatically, regardless of the setting of the rnzsel bit. caution the rnzc register can be set (written) only on ce after the reset signal is released. even if the register is written two or more ti mes, the first value written to it is not updated. to change the set value of the register, input the reset signal. chapter 22 reset function preliminary user?s manual u16895ej1v0ud 641 figure 22-4. sampling operation timing (20 times) oscillation stabilization time count period set by osts register internal reset signal (active low) reset signal f x 1 2 19 20 analog delay analog delay digital noise elimination <1> digital noise is eliminated when the rnzc.rnzsel bit = 1. <2> the reset pin is always sampled at the rising edge of the sampling clock (f x ). <3> if the reset pin goes low and is detected as lo w over the entire sampling timing, it is detected as an internal reset signal. because the analog noise eliminator is activated after digital noise has been eliminated, the internal reset signal is detected after analog delay. <4> when the internal reset signal is detected, t he rnzc register is initialized, so only the analog noise eliminator can be selected. (b) operation when sampling clock is stopped if the sampling clock (f x ) stops when the digital + analog noise eliminator is selected, input to the reset signal is not received. therefore, only the anal og noise eliminator is automatically selected. only the analog noise eliminator is automat ically selected during the following periods. ? in stop mode: setting of stop mode period to time set by the osts regist er that elapses after the stop mode is released (by a source other than reset) ? in subclock operation mode: setting of subclock operation mode (pcc.cls bit = 0 1) period until the main clock operation mode (cls bit = 1 0) is restored (c) digital noise elimination width the digital noise elimination width (t wrsl ) is as follows where t is the sampling clock period and n is the number of samplings. table 22-2. digital noise el imination width of reset pin digital noise elimination width (t wrsl ) t = 10 mhz , n = 20 t = 5 mhz , n = 10 operation t wrsl < ( n ? 1 ) t t wrsl < 1.9 s t wrsl < 1.8 s eliminated as noise ( n ? 1 ) t < t wrsl < nt 1.9 s t wrsl < 2.0 s 1.8 s t wrsl < 2.0 s may be eliminated as noise or detected as reset nt t wrsl 2.0 s t wrsl 2.0 s t wrsl detected as reset remark the noise on the reset pin is eliminated by a val ue that takes the value show n in this table and the analog delay value into consideration. chapter 22 reset function preliminary user?s manual u16895ej1v0ud 642 22.4.2 reset operati on by wdtres1 signal if a reset operation mode in which reset is effected when watchdog timer 1 overflows is set, the system is reset when watchdog timer 1 overflows (when the wdtres1 signal is generated), and each hardware unit is initialized to a specific status. after watchdog timer 1 has overflowed, the system is reset for a specific duration of time (f clk : 12 clocks) and then automatically released from the reset status. after releas e of the reset status, the cp u starts program execution. note that, because the main clock oscillator continues operating even during the re set period, the oscillation stabilization time is not secured. the following table shows the status of each hardware unit durin g the period of reset that is effected by the wdtres1 signal and after release of the reset status. table 22-3. hardware status on occurrence of wdtres1 signal item during reset after reset main clock oscillator (f x ) oscillation continues subclock oscillator (f xt ) oscillation continues ring-osc (f r ) oscillation continues peripheral clock (f xx to f xx /1024) operation stops operation starts internal system clock (f clk ) oscillation continues (initialized to f xx /8) cpu clock (f cpu ) oscillation continues (initialized to f xx /8) watchdog timer 1 clock (f xw ) operation continues internal ram undefined if writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value imm ediately before reset input is retained. i/o lines (p00) low-level output i/o lines (ports other than p00) high impedance on-chip peripheral i/o registers initialized to specified status watchdog timer 2 operation st ops operation starts (f r ) other on-chip peripheral fu nctions operation stops o peration can be started figure 22-5. timing of reset operation by watchdog timer 1 initialized to f xx /8 operation f clk : 12-clock width internal system reset signal (active low) wdtres1 signal (active low) f x f clk chapter 22 reset function preliminary user?s manual u16895ej1v0ud 643 22.4.3 reset operati on by wdtres2 signal if a reset operation mode in which reset is effected when watchdog timer 2 overflows is set, the system is reset when watchdog timer 2 overflows (when the wdtres2 signal is generated), and each hardware unit is initialized to a specific status. after watchdog timer 2 has overflowed, the system is reset for a specific duration of time (equivalent to analog delay) and then automatically released fr om the reset status. after release of the reset status, the oscillation stabilization time of the main clock oscillator is secured, and then the cpu st arts program execution. note that, because the main clock oscillator stops during t he reset period, the oscillation stabilization time must be secured. the oscillation stabilization ti me is determined by the default value of the osts register (for the oscillation stabilization time, refer to 21.2 (3) oscillation stabilizati on time selection register (osts) and chapter 28 mask option/option byte ). the status of each hardware unit duri ng the period of reset effected by the wdtres2 signal and after release of the reset status is the same as when re set is effected by the reset pin input. for details, refer to table 22-1 hardware status on reset pin input . the following figure shows the timing of the reset operation by the wdtres2 signal. figure 22-6. timing of reset operation by watchdog timer 2 oscillation stabilization time count initialized to f xx /8 operation overflow of oscillation stabilization time counter internal system reset signal (active low) wdtres2 signal (active low) f x f clk analog delay chapter 22 reset function preliminary user?s manual u16895ej1v0ud 644 22.4.4 power-on-clear reset operation the supply voltage (v dd ) and detection voltage (v poc ) are compared. when v dd < v poc , the system is reset and each hardware unit is initialized to a specific status. the detection voltage (v poc ) is 2.6 v 0.1 v. while v dd < v poc , the system is reset. reset is released when v dd v poc . after release of the reset status, the oscillation stabilization time of the ma in clock oscillator is secured, and then the cpu starts program execution. note that, because the main clock oscillator stops during t he reset period, the oscillation stabilization time must be secured. the oscillation stabilization ti me is determined by the default value of the osts register (for the oscillation stabilization time, refer to 21.2 (3) oscillation stabilizati on time selection register (osts) and chapter 28 mask option/option byte ). the following table shows the status of each hardware unit during the per iod of reset effected by the pocres signal and after release of reset. table 22-4. hardware status duri ng reset operation by power-on-clear item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues ring-osc (f r ) oscillation stops oscillation starts peripheral clock (f xx to f xx /1024) operation stops operation starts after securing oscillation stabilization time internal system clock (f clk ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) watchdog timer 1 clock (f xw ) operation stops operation starts cpu initialized program execution starts after securing oscillation stabilization time internal ram undefined if power-on reset or writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value imm ediately before reset input is retained. i/o lines (p00) low-level output i/o lines (ports other than p00) high impedance on-chip peripheral i/o registers initialized to specified status watchdog timer 2 operation st ops operation starts (f r ) other on-chip peripheral fu nctions operation stops operation can be started after securing oscillation stabilization time chapter 22 reset function preliminary user?s manual u16895ej1v0ud 645 figure 22-7. reset timing by power-on-clear circuit oscillation stabilization time count initialized to f xx /8 operation overflow of oscillation stabilization time counter internal system reset signal (active low) pocres signal (active low) f x f clk v dd v poc response time response time chapter 22 reset function preliminary user?s manual u16895ej1v0ud 646 figure 22-8. reset timing on power application oscillation stabilization time count initialized to f xx /8 operation overflow of oscillation stabilization time counter internal system reset signal (active low) pocres signal (active low) f x v dd v poc f clk response time chapter 22 reset function preliminary user?s manual u16895ej1v0ud 647 22.4.5 reset operation by low-voltage detector if a mode in which the internal reset signal (lvires) is to be generated by the low- voltage detector is set, the supply voltage (v dd ) and detection voltage (v lvi ) are compared. when v dd < v lvi , the system is reset and each hardware unit is initializ ed to a specific status. while v dd < v lvi , the system is reset. reset is released when v dd v lvi . after release of the reset status, the oscillation stabilization time of the ma in clock oscillator is secured, and then the cpu starts program execution. note that, because the main clock oscillator stops during t he reset period, the oscillation stabilization time must be secured. the oscillation stabilization ti me is determined by the default value of the osts register (for the oscillation stabilization time, refer to 21.2 (3) oscillation stabilizati on time selection register (osts) and chapter 28 mask option/option byte ). the status of each hardware unit during the period of reset effected by the lv ires signal and after release of reset is the same as when reset is effected by the pocres signal. figure 22-9. reset timing by low-voltage detector oscillation stabilization time count initialized to f xx /8 operation overflow of oscillation stabilization time counter internal system reset signal (active low) lvires signal (active low) f x f clk v dd v lvi response time response time v poc chapter 22 reset function preliminary user?s manual u16895ej1v0ud 648 22.4.6 reset operation by clock monitor if the main clock is monitored using the sampling clock (ring-osc: f r ) and if it is detected that the main clock has stopped when the clock monitor operation is enabled, the syst em is reset and each hardware unit is initialized to a specific status. after it is detected that the main clo ck stops, the system is reset for the durat ion of a specific time (equivalent to analog delay), and then the reset status is automatically released. after rele ase of the reset status, the timer for oscillation stabilization does not perform its counting operation because the main clock is stopped. if watchdog timer 2, which starts by default, overflows, the cpu starts program execution with ring-osc (f r ). the status of each hardware unit duri ng the period of reset effected by the clmres signal and after release of the reset status is shown below. for the timing of reset by t he clock monitor, refer to figure 23-4 . table 22-5. hardware status duri ng reset operation by clock monitor item during reset after reset main clock oscillator (f x ) oscillation stops oscillation remains stopped subclock oscillator (f xt ) oscillation continues ring-osc (f r ) oscillation stops oscillation starts peripheral clock (f xx to f xx /1024) operation stops operation remains stopped because f x is stopped internal system clock (f clk ) operation stops operation starts (f r ) after overflow of watchdog timer 2 cpu clock (f cpu ) operation stops operation starts (f r ) after overflow of watchdog timer 2 watchdog timer 1 clock (f xw ) operation stops operation remains stopped because f x is stopped cpu initialized program execution starts after overflow of watchdog timer 2 internal ram undefined if writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value imm ediately before reset input is retained. i/o lines (p00) low-level output i/o lines (ports other than p00) high impedance on-chip peripheral i/o registers initialized to specified status watchdog timer 2 operation stops operation starts (f r only). however, wdtres2 is not generated if watchdog timer 2 overflows before cpu execution. other on-chip peripheral fu nctions operation stops operation cannot be started because f x is stopped. however, the peripheral functions that operate on f xt , f r , or external clock can operate (for details, refer to table 23-2 ). chapter 22 reset function preliminary user?s manual u16895ej1v0ud 649 22.5 reset output function the p00/toh0 pin of the v8 50es/kf1+ can be used as a dummy reset output pin. the p00 pin is set in the output port mode (pm0.pm00 bit = 0) and outputs a low level (p0.p00 bit = 0) when the reset signal is generated. to rel ease the reset output (low-level output high-level output), set the p00 bit to 1 by software. figure 22-10. reset output function oscillation stabilization time count reset period p00 pin: output port mode p00 bit = 0 1 overflow of oscillation stabilization time counter reset signal (active low) p00/toh0 pin f x preliminary user?s manual u16895ej1v0ud 650 chapter 23 clock monitor 23.1 function the clock monitor samples the main clock by using the on-chip ring-osc clock and generates a reset signal (clmres) when oscillation of the main clock is stopped. after reset is released, t he cpu operates on ring-osc. once the operation of the clock monitor has been enabled by the clm.clme bit, it can be stopped only by reset. the clock monitor automatically stops under the following conditions. ? when the oscillation stabilization time is counted after the stop mode has been released ? when the main clock is stopped (pcc.mck bit = 1 w hen subclock operates and pcc.cls bit = 0 when main clock operates) ? when the sampling clock (ring-osc) is stopped ? when the cpu operates on ring-osc 23.2 registers (1) clock monitor mode register (clm) the clm register is a special register that can be written only by a combinat ion of specific sequences (refer to 3.4.7 special registers ). the clm register is used to select the operation mode of the clock monitor. this register can be read or written in 8-bit or 1-bit units. after reset, clm is cleared to 00h. 0 disable clock monitor operation enable clock monitor operation clme 0 1 enable/disable of clock monitor operation clm 0 0 0 0 0 0 clme after reset: 00h r/w address: fffff870h < > caution once the clme bit h as been set to 1, it cannot be cleared to 0 by any means other than reset. chapter 23 clock monitor preliminary user?s manual u16895ej1v0ud 651 (2) ring-osc mode register (rcm) the rcm register is an 8-bit register t hat sets the operation mode of ring-osc. this register can be read or written in 8-bit or 1-bit units. after reset, rcm is cleared to 00h. 0 rcm 0 0 0 00 0 rstop ring-osc oscillating ring-osc stopped rstop 0 1 oscillation/stop of ring-osc after reset: 00h r/w address: fffff80ch < > caution the setting of the rcm register is valid when stopping oscillation of ring-osc by software is enabled by the mask option/option byte. for details, refer to chapter 28 mask option/ option byte. chapter 23 clock monitor preliminary user?s manual u16895ej1v0ud 652 23.3 operation the clock monitor start and stop conditions are as follows. chapter 23 clock monitor preliminary user?s manual u16895ej1v0ud 653 (a) operation when main cl ock oscillation is stopped if oscillation of the main clock is stopped when the clme bit = 1, the clmres signal is generated as shown in figure 23-1. figure 23-1. when oscillation of main clock is stopped 4 ring-osc clocks main clock ring-osc clock clmres signal (active low) (b) operation in stop mode a nd after stop mode is released if the stop mode is set when the clme bit = 1, t he monitor operation is st opped in the stop mode and while the oscillation stabilization time is being counted. the monitor operation is automatically started after the oscillation stabilization time has elapsed. figure 23-2. operation in stop mode and after stop mode is released clock monitor status during monitoring monitor stops during monitoring clme bit ring-osc clock main clock cpu operation normal operation stop mode oscillation stabilization time normal operation oscillation stops oscillation stabilization time (set by osts register) chapter 23 clock monitor preliminary user?s manual u16895ej1v0ud 654 (c) operation when main clock is stopped (arbitrary) if the main clock is stopped by setting the pcc.mck bit to 1 while the subclock is operating (pcc.cls bit = 1), the monitor operation is stopped until the main clock operates (cls bit = 0). the monitor operation is automatically started when the main clock starts operating. figure 23-3. operation when main clock is stopped (arbitrary) clock monitor status during monitoring monitor stops monitor stops during monitoring clme bit ring-osc clock main clock cpu operation oscillation stops subclock operation main clock operation oscillation stabilization time (set by osts register) oscillation stabilization time counted by software mck bit = 1 (d) operation when cpu operates on ring-osc clock (ccls.cclsf bit = 1) the monitor operation is not started even if the cl me bit is set to 1 when the cclsf bit is 1. chapter 23 clock monitor preliminary user?s manual u16895ej1v0ud 655 23.4 ring clock operation mode 23.4.1 setting and operation status the ring clock operation mode is set by the clock moni tor function when the main clock oscillation frequency (f x ) is abnormal (stopped). in the ring clock operation mode, ring-osc (f r ) is supplied as the internal system clock (f clk ) and cpu clock (f cpu ). because the operating clock is ring-osc (f r ), it is recommended to reset the syst em once to set it in the normal operation mode. because the main clock oscillator (f x ) is stopped, only the internal peripheral functions that can operate on the subclock, ring clock, or external clock can continue operating. table 23-2 shows the operation status in the ring clock operation mode. 23.4.2 releasing ring clock operation mode the ring clock operation mode is replaced by the normal operation mode in which the main clock (f x ) oscillates when the system is reset. the ring clock operation mode cannot be released by software. figure 23-4. reset timing of clock monitor count operation or count stopped f x f clk f r clmres signal (active low) wdt2 count clme bit clmrf bit count operation continues stopped count operation f r operation oscillation stabilization time secured (count operation stops) main clock operation stopped watchdog timer 2 overflow (wdtres2 does not occur) watchdog timer 2 count operation starts main clock stop detected program fetch started remark software cannot be used to restore the normal ope ration mode from the ring clock operation mode. after reset (generation of the reset, wdtres2, pocres, or lvires signal), the normal operation mode can be restored only if the main clock (f x ) oscillates correctly. chapter 23 clock monitor preliminary user?s manual u16895ej1v0ud 656 table 23-2. operation status in ring clock operation mode operation status setting of ring clock operation mode item when subclock is not used when subclock is used rom correction operable interrupt controller operable 16-bit timer (tmp0) stops operation 16-bit timers (tm00, tm01) stops operation tm00: stops operation tm01: operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) operable when ti5m is selected as count clock operable when ti5m is selected as count clock or when inttm010 is selected as count clock and tm01 is enabled in ring clock operation mode timer h (tmh0) stops operation timer h (tmh1) operable when f r /2048 is selected as count clock watch timer stops operation operable when f xt is selected as count clock watchdog timer 1 stops operation watchdog timer 2 operable when f r is selected as count clock operable csi00, csi01 operable when sck0m input clock is selected as operation clock csia0 stops operation i 2 c0 note stops operation uart0 operable when asck0 is selected as count clock serial interface uart1 stops operation key interrupt function operable a/d converter stops operation real-time output operable when inttm5m is selected as real-t ime output trigger and tm5m is enabled in ring clock operation mode clock monitor stops operation power-on-clear operable low-voltage detector operable regulator operable port function operable external bus interface operable note only in the chapter 23 clock monitor preliminary user?s manual u16895ej1v0ud 657 23.5 ring halt mode 23.5.1 setting and operation status the ring halt mode is set when a dedicated instruction (h alt instruction) is executed in the ring clock operation mode. in the ring halt mode, the ring-osc oscillator continues operating. only clock supply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the ring halt mode was set. the on-chip peripheral functions that are in dependent of instruction processing by the cpu continue operating. the main clock oscillator (f x ) stops but the on-chip peripheral functions that can operate on the subclock (f xt ), ring-osc clock (f r ), or external clock continue operating. table 23-4 shows the operation status in the ring halt mode. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed with an unmasked interrupt requ est signal held pending, the system shifts to the ring halt mode, but th e ring halt mode is immediately released by the pending interrupt request signal. 23.5.2 releasing ring halt mode when the ring halt mode is re leased by an interrupt requ est signal, the ring clock operation mode is set. when the ring halt mode is released by reset, the norma l operation mode is restored if the main clock (f x ) oscillates correctly. (1) releasing ring halt mode by non- maskable interrupt request signal or unmasked maskable interrupt request signal the ring halt mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. if the ring halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower t han that of the interrupt request currently being serviced is issued, the ring halt mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt reques t currently being serviced is issued (including a non-maskable interrupt request signal), the ring halt mode is released and that interrupt request signal is acknowledged. table 23-3. operation after releasing ring halt mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed chapter 23 clock monitor preliminary user?s manual u16895ej1v0ud 658 (2) releasing ring halt mode by reset the same operation as the normal reset operation is performed. table 23-4. operation status in ring halt mode operation status setting of ring halt mode item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator stops operation subclock oscillator ? preliminary user?s manual u16895ej1v0ud 659 chapter 24 low-voltage detector 24.1 function the low-voltage detector (lvi) has the following functions. ? compares the supply voltage (v dd ) and detection voltage (v lv i ), and generates an interrupt request signal (intlvi) or reset signal (lvires) when v dd < v lv i . ? detection levels (seven levels) of supply voltage can be changed by software. ? interrupt or reset function can be selected by software. ? operable in stop mode. when the low-voltage detector is used to reset, the resf.lvi rf bit is set to 1 if the lvires signal is generated. for details of the resf register, refer to 22.3 (1) reset source flag register (resf) . 24.2 configuration a block diagram of the low-voltage detector is shown below. figure 24-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + detection voltage source ( v lvi ) v dd internal bus n-ch low-voltage detection level selection register (lvis) low-voltage detection register (lvim) lvis2 lvimd lvif intlvi internal reset signal ( lvires) 3 v dd low-voltage detection level selector selector chapter 24 low-voltage detector preliminary user?s manual u16895ej1v0ud 660 24.3 registers the low-voltage detector is controlle d by the following two registers. ? low-voltage detection register (lvim) ? low-voltage detection level selection register (lvis) (1) low-voltage detection register (lvim) the lvim register is an 8-bit register that se ts the operation mode of the low-voltage detector. the lvim register is a special register that can be written only by a combinat ion of specific sequences (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit uni ts. if the lvion and lvimd bits = 11, however, the lvim register cannot be rewritten until the reset signal (lvires) is generated. the lvim register is reset to 00h by a reset source other than the low-voltage detec tor. the lvim register holds its value when reset is effected by the low-voltage detector. lvion lvion 0 1 disable operation enable operation lvim 0 0 0 0 0 lvimd lvif note 2 after reset: 00h note 1 r/w address: fffff890h enable/disable low-voltage detection operation lvif note 2 0 1 supply voltage (v dd ) > detection voltage (v lvi ), or when operation is disabled supply voltage (v dd ) < detection voltage (v lvi ) low-voltage detection flag lvimd 0 1 generate interrupt request signal (intlvi) when supply voltage (v dd ) < detection voltage generate internal reset signal (lvires) when supply voltage (v dd ) < detection voltage low-voltage detection operation mode selection < > < > < > notes 1. the lvim register holds its value when rese t is effected by the low-voltage detector. 2. the lvif bit is read-only. caution be sure to clear bits 6 to 2 to 0. remark the value of the lvif bit is out put as the interrupt request signal (intlvi) when the lvion bit = 1 and lvimd bit = 0. chapter 24 low-voltage detector preliminary user?s manual u16895ej1v0ud 661 (2) low-voltage detection level selection register (lvis) the lvis register is an 8-bit register t hat selects the low-voltage detection level. the lvis register can be read or written in 8-bit unit s. if the lvim.lvion and lvim.lvimd bits = 11, however, the lvis register cannot be rewritten until the reset signal (lvires) is generated. the lvis register is reset to 00h by a reset source other than the low-voltage detector. the lvis register holds its value when reset is effected by the low-voltage detector. 0 lvis2 0 0 0 0 1 1 1 lvis1 0 0 1 1 0 0 1 other than above lvis0 0 1 0 1 0 1 0 4.3 v 0.2 v 4.1 v 0.2 v 3.9 v 0.2 v 3.7 v 0.2 v 3.5 v 0.2 v 3.3 v 0.15 v 3.1 v 0.15 v setting prohibited lvis 0 0 0 0 lvis2 lvis1 lvis0 after reset: 00h note r/w address: fffff891h detection level note the lvis register holds its value when rese t is effected by the low-voltage detector. caution be sure to clear bits 7 to 3 to 0. chapter 24 low-voltage detector preliminary user?s manual u16895ej1v0ud 662 24.4 operation the low-voltage detector can be used in the following two modes. ? reset operation (lvires): compares the supply voltage (v dd ) and detection voltage (v lv i ), and generates a reset signal (lvires) when v dd < v lv i . ? interrupt operation (intlvi): compares the supply voltage (v dd ) and detection voltage (v lv i ), and generates an interrupt request signal (intlvi) when v dd < v lv i . (1) reset operation (lvires) chapter 24 low-voltage detector preliminary user?s manual u16895ej1v0ud 663 (2) interrupt operation (intlvi) preliminary user?s manual u16895ej1v0ud 664 chapter 25 power-on-clear circuit 25.1 function the power-on-clear (poc) circuit has the following functions. ? generates a reset signal (pocres) upon power application. ? compares the supply voltage (v dd ) and detection voltage (v poc ), and generates a reset signal (pocres) when v dd < v poc (detection voltage: v poc = 2.6 v 0.1 v). caution if the pocres signal is generated by the poc circuit, the resf regist er is cleared (to 00h). 25.2 configuration a block diagram of the power-on-clear circuit is shown below. figure 25-1. block diagram of power-on-clear circuit ? + detection voltage source ( v poc ) reset signal ( pocres) v dd chapter 25 power-on-clear circuit preliminary user?s manual u16895ej1v0ud 665 25.3 operation the power-on-clear circuit compares the supply voltage (v dd ) and detection voltage (v poc ), and generates a reset signal (pocres) when v dd < v poc . figure 25-2. operation of power-on-clear circuit supply voltage ( v dd ) power-on-clear circuit detection voltage ( v poc ) 2.5 v pocres signal (active low) preliminary user?s manual u16895ej1v0ud 666 chapter 26 regulator 26.1 overview the v850es/kf1+ includes a regulator to re duce the power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits (except the a/d converter and output buffer). the regulator output vo ltage is set to 3.6 v (typ.). figure 26-1. regulator ev dd i/o buffer (normal port) 2.7 to 5.5 v bidirectional level shifter regulator a/d converter 2.7 to 5.5 v av ref0 v pp v dd ev dd regc flash memory main/sub oscillator internal digital circuits 3.6 v (typ.) caution use the regulator with a setting of v dd = ev dd = av ref0 . 26.2 operation the regulator stops operating in the foll owing modes (but only when regc = v dd ). ? at reset (except wdtres1 and during oscillation stabilization time) ? in stop mode ? in sub-idle mode when using the regulator, be sure to connect a capacitor (10 f) to the regc pin to stabilize the regulator output. a diagram of the regulator pin connections is shown below. chapter 26 regulator preliminary user?s manual u16895ej1v0ud 667 figure 26-2. regc pin connection (a) when regc = v dd reg input voltage = 2.7 to 5.5 v voltage supply to oscillator/internal logic = 2.7 to 5.5 v v dd regc (b) when connecting regc pin to v ss via a capacitor reg input voltage = 4.0 to 5.5 v voltage supply to oscillator/internal logic = 3.6 v v dd regc 10 f (recommended) v ss preliminary user?s manual u16895ej1v0ud 668 chapter 27 rom correction function 27.1 overview the rom correction function is used to replace part of the program in the internal rom with the program of an external memory or the internal ram. by using this function, program bugs foun d in the internal rom can be corrected. up to four addresses can be specified for correction. figure 27-1. block diag ram of rom correction instruction address bus block replacing bug with dbtrap instruction instruction data bus internal rom dbtrap instruction generation block correction address register n (coradn) correction control register (corenn bit) comparator remark n = 0 to 3 chapter 27 rom correction function preliminary user?s manual u16895ej1v0ud 669 27.2 control registers 27.2.1 correction address regist ers 0 to 3 (corad0 to corad3) these registers are used to set the firs t address of the program to be corrected. the program can be corrected at up to four places because four coradn registers are provided. the coradn register can be read or writte n in 32-bit units. if the higher 16 bits of the coradn register are used as the coradnh register, and the lower 16 bits as the coradnl register, these registers can be read or written in 16-bit units. after reset, coradn is cleared to 00000000h. set correction addresses in the following ranges. pd70f3306, 70f3306y (128 kb): 0000000h to 001fffeh pd703308, 703308y, 70f3 308, 70f3308y (256 kb): 0000000h to 003fffeh correction address fixed to 0 0 coradn (n = 0 to 3) after reset: 00000000h r/w address: refer to table 27-1 31 16 17 19 20 1 0 note correction address fixed to 0 0 coradn (n = 0 to 3) 31 17 18 19 20 1 0 note (a) 128 kb (b) 256 kb note be sure to clear these bits to 0. table 27-1. coradn address address register name address register name fffff840h corad0 fffff848h corad2 fffff840h corad0l fffff848h corad2l fffff842h corad0h fffff84ah corad2h fffff844h corad1 fffff84ch corad3 fffff844h corad1l fffff84ch corad3l fffff846h corad1h fffff84eh corad3h chapter 27 rom correction function preliminary user?s manual u16895ej1v0ud 670 27.2.2 correction control register (corcn) this register disables or enables the correction oper ation at the address specifie d by the coradn register. each channel can be enabled or disabled by this register. this register can be read or written in 8-bit or 1-bit units. after reset, corcn is cleared to 00h. 0 disabled enabled corenn 0 1 correction operation enable/disable corcn 0 0 0 coren3 coren2 coren1 coren0 after reset: 00h r/w address: fffff880h < > < > < > < > remark n = 0 to 3 table 27-2. correspondence between corcn register bits and coradn registers corcn register bit corresponding coradn register coren3 corad3 coren2 corad2 coren1 corad1 coren0 corad0 27.3 rom correction operation and program flow <1> if the address to be corrected and the fetch address of t he internal rom match, the fetch code is replaced by the dbtrap instruction. <2> when the dbtrap instruction is execut ed, execution branches to address 00000060h. <3> software processing after branching causes the result of rom correction to be judged (the fetch address and rom correction operation are confirmed) and exec ution to branch to the correction software. <4> after the correction software has been executed, the return address is set, and return processing is started by the dbret instruction. cautions 1. the software that performs <3> a nd <4> must be executed in the internal ram. 2. when setting an address to be corrected to the coradn register, clear the higher bits to 0 in accordance with the capacity of the internal rom. 3. the rom correction function cannot be used to correct the data of the internal rom. it can only be used to correct instructi on codes. if rom correction is u sed to correct data, that data is replaced with the dbtrap instruction code. chapter 27 rom correction function preliminary user?s manual u16895ej1v0ud 671 figure 27-2. rom correction operation and program flow reset & start fetch address = coradn? coradn = dbpc ? 2? corenn bit = 1? initialize microcontroller set coradn register change fetch code to dbtrap instruction branch to rom correction judgment address branch to correction code address of corresponding channel n execute fetch code read data for setting rom correction from external memory execute dbtrap instruction jump to address 00000060h execute correction code execute dbret instruction write return address to dbpc. write value of psw to dbpsw as necessary. set corcn register yes yes yes no no remarks 1. : processing by user program (software) 2. n = 0 to 3 : processing by rom correction (hardware) load program for judgment of rom correction and correction codes execute fetch code ilgop processing no preliminary user?s manual u16895ej1v0ud 672 chapter 28 mask option/option byte 28.1 mask option (mask rom versions) the mask rom versions ( pd703308 and 703308y) have the following mask options. ? connection of pull-up resistor to p38 and p39 pins ? enabling/disabling stopping ring-osc by software ? shortening oscillation stabilization time of main clock oscillation after release of reset (1) connection of pull-up resistor to p38 and p39 pins pumn connection of pull-up resistor to port mn 0 not connected 1 connected remark mn = 38, 39 (2) enabling/disabling stop ping ring-osc by software ringstp control of stopping ring-osc by software 0 can be stopped by software 1 setting invalid by software depending on whether the option to enable/disable stopping of ring-osc by software is set or not, the operation differs as follows. table 28-1. option to enable/disable stopping of ring-osc by software ringstp = 0 (can be stopped) ringstp = 1 (setting invalid) ring-osc ring-osc: can be stopped. rcm.rstop bit can be set. ring-osc: cannot be stopped. setting of rstop bit is invalid. count operation operation can be stopped by wdtm2.wdcs24 bit. operation cannot be stopped. input clock the following clock can be selected by the wdtm2 register. ? ring-osc: f r /8 ? subclock: f xt fixed to ring-osc (f r /8) wdt2 operation mode the following mode can be selected by the wdtm2 register. ? nmi interrupt mode (intwdt2) ? reset mode (wdtres2) fixed to reset mode (wdtres2) chapter 28 mask option/option byte preliminary user?s manual u16895ej1v0ud 673 (3) shortening oscillation stabili zation time of main clock osc illation after release of reset option to shorten oscillation stabilization time of main clock oscillation after release of reset osts0 (default value of osts register) oscillation stabilization time 0 shorten oscillation stabilization time. 00h 2 13 /f x 1 do not shorten oscillation stabilization time. 01h 2 15 /f x 28.2 option byte (flash memory versions) the flash memory versions ( pd70f3306, 70f3306y, 70f3308, and 70f330 8y) can realize the mask options of the mask rom version by using an option byte (except the pull-up resistor option). the option byte is stored in address 0 00007ah of the internal flash memory (internal rom area) as 8-bit data. ? osts0 note 1 shorten oscillation stabilization time (default value of osts register = 00h) do not shorten oscillation stabilization time (default value of osts register = 01h) ?? osts0 ?? ? ringstp address: 0000007ah option to shorten oscillation stabilization time of main clock oscillation after release of reset ringstp note 2 0 1 can be stopped by software cannot be stopped by software option to enable/disable stopping ring-osc by software 0 1 notes 1. for details of the option, refer to 28.1 (3) shortening oscillation st abilization time of main clock oscillation after release of reset . 2. for details of t he option, refer to table 28-1 option to enable/disable stopping of ring-osc by software . preliminary user?s manual u16895ej1v0ud 674 chapter 29 flash memory the following products are the flash me mory versions of the v850es/kf1+. caution there are differences in noise immunity a nd noise radiation between th e flash memory and mask rom versions. when pre-producing and applicati on set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluation for the commercial samples (not engineering samples) of the mask rom version. for the electrical specifications related to the flash memory rewriting, refer to chapter 30 electrical specifications (target). ? pd70f3306, 70f3306y: on-chip 128 kb flash memory ? pd70f3308, 70f3308y: on-chip 256 kb flash memory flash memory versions are commonly used in the following development environments and mass production applications. { for altering software after the v850es/kf 1+ is soldered onto the target system. { for data adjustment when starting mass production. { for differentiating software according to the specif ication in small scale production of various models. { for facilitating inventory management. { for updating software after shipment. 29.1 features { 4-byte/1-clock access (when instruction is fetched) { capacity: 128/256 kb { write voltage: erase/write with a single power supply { rewriting method ? rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { flash memory write prohibit f unction supported (security function) { safe rewriting of entire flash memory area by self programming using boot swap function { interrupts can be acknowledged during self programming. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 675 29.2 memory configuration the 128/256 kb internal flash memory area is divided in to 64/128 blocks and can be programmed/erased in block units. all the blocks can also be erased at once. when the boot swap function is used, the physical memory (blocks 0 to 3) located at the addresses of boot area 0 is replaced by the physical memory (blocks 4 to 7) locate d at the addresses of boot area 1. for details of the boot swap function, refer to 29.5 rewriting by self programming . figure 29-1. flash memory mapping block 0 (2 kb) block 1 (2 kb) block 2 (2 kb) block 3 (2 kb) block 5 (2 kb) block 6 (2 kb) block 7 (2 kb) block 8 (2 kb) block 4 (2 kb) block 63 (2 kb) block 125 (2 kb) block 127 (2 kb) block 126 (2 kb) block 0 (2 kb) block 1 (2 kb) block 2 (2 kb) block 3 (2 kb) block 5 (2 kb) block 6 (2 kb) block 7 (2 kb) block 8 (2 kb) block 4 (2 kb) block 63 (2 kb) use prohibited external memory area (64 kb) external memory area (64 kb) internal flash memory area (256/128 kb) use prohibited boot area 0 note (8 kb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) boot area 1 note (8 kb) 3fff fffh 3fec000h 3feb fffh 003f fffh 003f800h 003f 7ffh 003f000h 003e fffh 003e800h 003e 7ffh 0020000h 001f fffh 0005000h 0004 fffh 0004800h 0004 7ffh 0003800h 0003 7ffh 0003000h 0002 fffh 0002800h 0002 7ffh 0001800h 0001 7ffh 0001000h 0000 fffh 0000000h 0000800h 0000 7ffh 0002000h 0001 fffh 0004000h 0003 fffh 3ff0000h 3feffffh 0210 000h 020f fffh 0110000h 010f fffh 0100000h 00fffffh 0000000h use prohibited 0200000h 01ff fffh note boot area 0 (blocks 0 to 3): boot area boot area 1 (blocks 4 to 7): area used to replace boot area via boot swap function chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 676 29.3 functional outline the internal flash memory of the v850es/kf1+ can be rewri tten by using the rewrite func tion of the dedicated flash programmer, regardless of whether the v850es/kf1+ has already been mounted on the target system or not (on- board/off-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programmi ng) is ideal for an application where it is assumed that the program is changed after production/sh ipment of the target syst em. a boot swap function t hat rewrites the entire flash memory area safely is also supported. in addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten und er various conditions, such as while communicating with an external device. table 29-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/off- board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance). normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 677 table 29-2. basic functions support ( { : supported, : not supported) function functional outline on-board/off-board programming self programming block erasure the contents of specified memory blocks are erased. { { chip erasure the contents of the entire memory area are erased all at once. { write writing to specified addresses, and a verify check to see if write level is secured are performed. { { verify/checksum data read from the flash memory is compared with data transferred from the flash programmer. { (can be read by user program) blank check the erasure status of the entire memory is checked. { { security setting use of the block erase command, chip erase command, and program command can be prohibited. { (only values set by on- board/off-board programming can be retained) the following table lists the security functions. the bl ock erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. each security function can be used in combination with the others at the same time. table 29-3. security functions rewriting operation when prohibited ( { : executable, : not executable) function functional outline on-board/off-board programming self programming block erase command prohibit execution of a block erase command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. block erase command: chip erase command: { program command: { chip erase command prohibit execution of block erase and chip erase commands on all the blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. block erase command: chip erase command: program command: { program command prohibit write and block erase commands on all the blocks are prohibited. setting of prohibition can be initialized by execution of the chip erase command. block erase command: chip erase command: { program command: can always be rewritten regardless of setting of prohibition chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 678 29.4 rewriting by dedicated flash programmer the flash memory can be rewritten by using a dedica ted flash programmer after the v850es/kf1+ is mounted on the target system (on-board pr ogramming). the flash memory can also be re written before the device is mounted on the target system (off-board progr amming) by using a dedicated program adapter (fa series). 29.4.1 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850es/kf1+. figure 29-2. environment required fo r writing programs to flash memory host machine rs-232c dedicated flash programmer v850es/kf1+ flmd1 v dd v ss reset uart0/csi00 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve flmd0 usb a host machine is required for controlling the dedicated flash programmer. uart0 or csi00 is used for the in terface between the dedicated flash programmer and the v850es/kf1+ to perform writing, erasing, etc. a dedicated program adapter (fa series) is required for off-board writing. remark the fa series is a product of na ito densei machida mfg. co., ltd. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 679 29.4.2 communication mode communication between the dedicated flash programm er and the v850es/kf1+ is performed by serial communication using the uart0 or csi 00 interfaces of the v850es/kf1+. (1) uart0 transfer rate: 9,600 to 153,600 bps figure 29-3. communication with dedicated flash programmer (uart0) dedicated flash programmer v850es/kf1+ v dd v ss reset txd0 rxd0 flmd1 flmd1 flmd0 flmd0 v dd gnd reset rxd txd x1 x2 clk pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve (2) csi00 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 29-4. communication with de dicated flash programmer (csi00) dedicated flash programmer v850es/kf1+ flmd1 v dd v ss reset so00 si00 sck00 flmd1 flmd0 flmd0 v dd gnd reset si so sck pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve x1 x2 clk chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 680 (3) csi00 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 29-5. communication with dedi cated flash programmer (csi00 + hs) dedicated flash programmer v850es/kf1+ v dd v ss reset so00 si00 sck00 pcm0 v dd flmd1 flmd1 flmd0 flmd0 gnd reset si so sck hs pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx y yy x x x x x x x x x x x x x x x xxxx y y yy statve x1 x2 clk the dedicated flash programmer outputs the transfer clock, and the v850es/kf1+ operates as a slave. when the pg-fp4 is used as the d edicated flash programmer, it gener ates the following signals to the v850es/kf1+. for details, refer to the pg-fp4 user?s manual (u15260e) . table 29-4. signal connections of dedicated flash programmer (pg-fp4) pg-fp4 v850es/kf1+ processing for connection signal name i/o pin function pin name uart0 csi00 csi00 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/kf1+ x1, x2 note 2 note 2 note 2 reset output reset signal reset si/rxd input receive signal so00, txd0 so/txd output transmit signal si00, rxd0 sck output transfer clock sck00 hs input handshake signal for csi00 + hs communication pcm0 notes 1. wire the pin as shown in figure 29-6, or connect it to gnd on board via a pull-down resistor. 2. connect these pins to supply a clock from the pg -fp4 (wire as shown in figure 29-6, or create an oscillator on board and supply the clock). remark : must be connected. : does not have to be connected. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 681 table 29-5. wiring between pd70f3306, 70f3306y, 70f3308, and 70f3308y, and pg-fp4 pin configuration of flash programmer (pg-fp4) with csi00-hs with csi00 with uart0 signal name i/o pin function pin name on fa board pin name pin no. pin name pin no. pin name pin no. si/r x d input receive signal si p41/ so00 20 p41/so00 20 p30/txd0 22 so/t x d output transmit signal so p40/si00 19 p40/si00 19 p31/rxd0/ intp7 23 sck output transfer clock sck p42/sck00 21 p42/sck00 21 not needed not needed x1 x1 12 x1 12 x1 12 clk output clock to v850es/kf1+ x2 x2 note 13 x2 note 13 x2 note 13 /reset output reset signal /reset reset 14 reset 14 reset 14 flmd0 input write voltage flmd0 flmd0 8 flmd0 8 flmd0 8 flmd1 input write voltage flmd1 pdl5/ad5/ flmd1 62 pdl5/ad5/ flmd1 62 pdl5/ad5/ flmd1 62 hs input handshake signal for csi00 + hs communication reserve/hs pcm0/ wait 49 not needed not needed not needed not needed v dd 9 v dd 9 v dd 9 ev dd 31 ev dd 31 ev dd 31 vdd ? v dd voltage generation/ voltage monitor vdd av ref0 1 av ref0 1 av ref0 1 v ss 11 v ss 11 v ss 11 av ss 2 av ss 2 av ss 2 gnd ? ground gnd ev ss 30 ev ss 30 ev ss 30 note when using the clock out of the flash programmer, c onnect clk of the programmer to x1, and connect its inverse signal to x2. cautions 1. be sure to connect the regc pin in either of the following ways. ? connect to gnd via a 10 f capacitor ? directly connect to v dd 2. when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by creating an oscillator on the board. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 682 figure 29-6. wiring example of v850es/kf1+ fl ash writing adapter (fa- 80gc-8bt, fa-80gk-9eu) rfu-3 rfu-2 rfu-1 flmd1 flmd0 vde pd70f3306h, pd70f3306hy, pd70f3308h, pd70f3308hy vdd gnd gnd vdd gnd vdd vdd gnd 31 connect to vdd. connect to gnd. 1 9 8 2 11 12 13 14 49 62 19 20 30 21 so sck si x1 /reset v pp reserve/hs x2 10 note 2 note 1 notes 1. wire the flmd1 pin as shown in the figure, or c onnect it to gnd on board via a pull-down resistor. 2. be sure to connect the regc pin in either of the following ways. ? connect to gnd via a 10 f capacitor. ? directly connect to v dd . when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by creati ng an oscillator on the board. remarks 1. handle the pins not described above in accord ance with the specified handling of unused pins (refer to 2.3 pin i/o circuits and recomm ended connection of unused pins) . when connecting to v dd via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for an 80-pin plastic tqfp (fine pitch) or 80-pin plastic qfp package. 3. this diagram shows the wiring when using a handshake-supporting csi. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 683 29.4.3 flash memory control the following shows the procedure for manipulating the flash memory. figure 29-7. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 684 29.4.4 selection of communication mode in the v850es/kf1+, the communication mode is selected by inputting pulses (12 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. figure 29-8. selection of communication mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxd0 (input) txd0 (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released note the number of clocks is as follows depending on the communication mode. flmd0 pulse communication mode remarks 0 uart0 communication rate: 9600 bps (after reset), lsb first 8 csi00 v850es/kf1+ performs slave operation, msb first 11 csi00 + hs v850es/kf1+ performs slave operation, msb first other rfu setting prohibited caution when uart0 is selected, the receive clock is calculate d based on the reset command sent from the dedicated flash programme r after receiving the flmd0 pulse. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 685 29.4.5 communication commands the v850es/kf1+ communicates with the dedicated flash programmer by means of commands. the signals sent from the dedicated flash programmer to the v850es/kf1+ are called ?commands?. the response signals sent from the v850es/kf1+ to the dedicated flash programmer are called ?response commands?. figure 29-9. communication commands dedicated flash programmer v850es/kf1+ command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve the following shows the commands for flash memory cont rol in the v850es/kf1+. all of these commands are issued from the dedicated flash progr ammer, and the v850es/kf1+ performs the processing corresponding to the commands. table 29-6. flash memory control commands support classification command name csi00 csi00 + hs uart0 function blank check block blank check command { { { checks if the contents of the memory in the specified block have been correctly erased. chip erase command { { { erases the contents of the entire memory. erase block erase command { { { erases the contents of the memory of the specified block. write write command { { { writes the specified address range, and executes a contents verify check. verify command { { { compares the contents of memory in the specified address range with data transferred from the flash programmer. verify checksum command { { { reads the checksum in the specified address range. silicon signature command { { { reads silicon signature information. system setting, control security setting command { { { disables the chip erase command, enables the block erase command, and disables the write command. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 686 29.4.6 pin connection when performing on-board writing, mount a connector on t he target system to conne ct to the dedicated flash programmer. also, incorporate a function on-board to s witch from the normal operation mode to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after rese t. therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mode, input a voltage of v ss level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, refer to 29.5.5 (1) flmd0 pin . figure 29-10. flmd0 pin connection example v850es/kf1+ flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 ) chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 687 (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 29-11. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/kf1+ caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. table 29-7. relationship between flmd0 and flmd1 pi ns and operation mode wh en reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 688 (3) serial interface pin the following shows the pins used by each serial interface. table 29-8. pins used by serial interfaces serial interface pins used uart0 txd0, rxd0 csi00 so00, si00, sck00 csi00 + hs so00, si00, sck00, pcm0 when connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) conflict of signals when the dedicated flash programmer (output) is connec ted to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. figure 29-12. conflict of signals (serial interface input pin) v850es/kf1+ input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 689 (b) malfunction of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 29-13. malfunction of other device v850es/kf1+ pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/kf1+ outputs affects the other device, isolate the signal on the other device side. v850es/kf1+ pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 690 (4) reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signal s occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 29-14. conflict of signals (reset pin) v850es/kf1+ reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. (5) port pins (including nmi) when the system shifts to the flash memory programmi ng mode, all the pins that are not used for flash memory programming are in the same st atus as that immediately after rese t. if the external device connected to each port does not recognize the st atus of the port immediately after reset, pins require appropriate processing, such as connecting to v dd via a resistor or connecting to v ss via a resistor. (6) other signal pins connect x1, x2, xt1, xt2, and regc in the same status as that in t he normal operation mode. (7) power supply supply the same power (v dd , v ss , ev dd , ev ss , av ss , av ref0 ) as in normal operation mode. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 691 29.5 rewriting by self programming 29.5.1 overview the v850es/kf1+ supports a flash macro service that allo ws the user program to rewrite the internal flash memory by itself. by using this interface and a self progra mming library that is used to rewrite the flash memory with a user application program, the flash me mory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, t he user program can be upgraded and constant data can be rewritten in the field. figure 29-15. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 692 29.5.2 features (1) secure self programming (boot swap function) the v850es/kf1+ supports a boot swap function that can exchange the physi cal memory (blocks 0 to 3) of boot area 0 with the physical memory (blocks 4 to 7) of boot area 1. by writi ng the start program to be rewritten to boot area 1 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriti ng because the correct user program always exists in boot area 0. figure 29-16. rewriting entire memory area (boot swap) block n block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 block n block n boot swap rewriting boot areas 0 and 1 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 remark pd70f3306, 70f3306y: n = 63 pd70f3308, 70f3308y: n = 127 (2) interrupt support instructions cannot be fetched from the flash memory during self programming. c onventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. with the v850es/kf1+, a user handler can be registered to an ent ry ram area by using a li brary function, so that interrupt servicing can be performed by inte rnal ram or external memory execution. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 693 29.5.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 29-17. standard self programming flow flash environment initialization processing erase processing write processing flash information setting processing note 1 internal verify processing boot area swapping processing note 2 flash environment end processing flash memory manipulation end of processing all blocks end? ? disable accessing flash area ? disable setting of stop mode ? disable stopping clock yes no notes 1. if a security setting is not performed, flash in formation setting processing does not have to be executed. 2. if boot swap is not used, flash information setting processing and boot area swap processing do not have to be executed. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 694 29.5.4 flash functions table 29-9. flash function list function name outline support flashenv initialization of flash control macro flashblockerase erasure of only specified one block flashwordread reading data from specified address flashwordwrite writing from specified address flashblockiverify internal verification of specified block flashblockblankcheck blank check of specified block flashflmdcheck check of flmd pin flashgetinfo reading of flash information flashsetinfo setting of flash information flashbootswap swapping of boot area 29.5.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode when re set is released and to protect the flash memory from being written during self rewriting. it is therefore necessary to keep the voltage applied to the flmd0 pin at 0 v when reset is released and a normal operation is exec uted. it is also necessary to apply a voltage of v dd level to the flmd0 pin during the self programming m ode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 29-18. mode change timing reset signal flmd0 pin v dd 0 v v dd 0 v self programming mode normal operation mode normal operation mode caution make sure that the flmd0 pin is at 0 v when reset is released. chapter 29 flash memory preliminary user?s manual u16895ej1v0ud 695 29.5.6 internal resources used the following table lists the internal resources used for se lf programming. these internal resources can also be used freely for purposes ot her than self programming. table 29-10. internal resources used resource name description entry ram area (internal ram/external ram size note ) routines and parameters used for the flash macr o service are located in this area. the entry program and default parameters are copied by calling a library initialization function. stack area (stack size note ) an extension of the stack used by the user is used by the library (can be used in both the internal ram and external ram). library code (code size note ) program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in user application execut ion status or self programming status. to use this interrupt in the self programming status, the interrupt servicing start address must be registered in advance by a registration function. nmi interrupt can be used in user application execution status or self programming status. to use this interrupt in the self programming status, the interrupt servicing start address must be registered in advance by a registration function. tm50, tm51 because tm50 and tm51 are used in the flash macro service, do not use them in the self programming status. when using tm50 and tm51 after self programming, set them again. note for the capacity to be used, refer to the v850 series flash memory se lf programming (single power supply flash memory) user?s manual (under preparation). preliminary user?s manual u16895ej1v0ud 696 chapter 30 electrical specifications (target) absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 ? 0.3 to +6.5 v av ref0 v dd = ev dd = av ref0 ? 0.3 to +6.5 v ev dd v dd = ev dd = av ref0 ? 0.3 to +6.5 v v ss v ss = ev ss = av ss ? 0.3 to +0.3 v av ss v ss = ev ss = av ss ? 0.3 to +0.3 v supply voltage ev ss v ss = ev ss = av ss ? 0.3 to +0.3 v v i1 p00 to p06, p30 to p35, p38, p39, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15, reset, flmd0 ? 0.3 to ev dd + 0.3 note v input voltage v i2 x1, x2, xt1, xt2 ? 0.3 to v dd + 0.3 note v analog input voltage v ian p70 to p77 ? 0.3 to av ref0 + 0.3 note v note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 697 absolute maximum ratings (t a = 25 ? ? ? ? ? ? ? chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 698 operating conditions (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 0.25 20 mhz regc = v dd = 4.0 to 5.5 v 0.25 16 mhz regc = capacity, v dd = 4.0 to 5.5 v 0.25 8 note mhz in pll mode regc = v dd = 2.7 to 5.5 v 0.25 8 note mhz regc = v dd = 4.0 to 5.5 v 0.0625 10 mhz regc = capacity, v dd = 4.0 to 5.5 v 0.0625 8 note mhz in clock-through mode regc = v dd = 2.7 to 5.5 v 0.0625 8 note mhz operating with subclock regc = v dd = 2.7 to 5.5 v 32.768 khz internal system clock frequency f clk operating with on-chip ring clock regc = v dd = 2.7 to 5.5 v 120 240 480 khz note these values may change after evaluation. internal system clock fr equency vs. supply voltage 1.0 0.1 0.032 0.01 supply voltage v dd [v] when regc = capacity internal system clock frequency f clk [mhz] 2.0 10.0 8.0 20.0 100 3.0 4.0 5.0 5.5 4.5 6.0 chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 699 main clock oscilla tor characteristics (1) crystal resonator, ceramic resonator (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 2 5 mhz regc = v dd = 4.0 to 5.5 v 2 4 mhz regc = capacity, v dd = 4.0 to 5.5 v 2 2 note 2 mhz pll mode regc = v dd = 2.7 to 5.5 v 2 2.5 mhz oscillation frequency (f x ) note 1 clock-through mode v dd = 2.7 to 5.5 v 2 10 mhz when osts0 note 4 = 0 2 13 /f x s after reset is released when osts0 note 4 = 1 2 15 /f x s x2 x1 oscillation stabilization time note 3 after stop mode is released note 5 s notes 1. indicates only oscillator characteristics. 2. this value may change after evaluation. 3. time required to stabilize the resonator after reset or stop mode is released. 4. set by mask option/option byte (refer to chapter 28 ). 5. the value differs depending on the osts register settings. (2) external clock (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 2 5 mhz regc = v dd = 4.0 to 5.5 v 2 4 mhz pll mode note regc = v dd = 2.7 to 5.5 v 2 2.5 mhz external clock x2 x1 input frequency (f x ) clock-through mode note v dd = 2.7 to 5.5 v 2 10 mhz note make sure that the duty ratio of the input waveform is within 50% 5%. cautions 1. when using the main cl ock oscillator, wire as follows in the area enclosed by th e broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. when the main clock is stopped and the devi ce is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 700 subclock oscillator characteristics (1) crystal resonator (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz xt2 xt1 oscillation stabilization time note 2 10 s notes 1. indicates only oscillator characteristics. 2. time required from when v dd reaches oscillation voltage range (2 .7 v (min.)) to when the crystal resonator stabilizes. (2) external clock (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit external clock xt2 xt1 input frequency (f xt ) regc = v dd 32 35 khz cautions 1. when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avo id an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-am plitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillato r. particular care is therefore required with the wiring me thod when the subclock is used. 3. make sure that the duty ratio of the input waveform is within 50% 5%. ring-osc characteristics (t a = ? 40 to + 85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit ring-osc frequency f r 120 240 480 khz pll characteristics (t a = ? 40 to + 85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency f x 2 5 mhz output frequency f xx 8 20 mhz lock time t pll after v dd reaches 2.7 v (min.) 200 s chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 701 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (1/5) parameter symbol conditions min. typ. max. unit per pin for p00 to p06, p30 to p35, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 ? 5.0 ma ev dd = 4.0 to 5.5 v ? 30 ma total of p00 to p06, p30 to p35, p40 to p42 ev dd = 2.7 to 5.5 v ? 15 ma ev dd = 4.0 to 5.5 v ? 30 ma output current, high i oh1 total of p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 ev dd = 2.7 to 5.5 v ? 15 ma per pin for p00 to p06, p30 to p35, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 10 ma ev dd = 4.0 to 5.5 v 15 ma per pin for p38, p39 ev dd = 2.7 to 5.5 v 8 ma total of p00 to p06, p30 to p35, p40 to p42 30 ma output current, low i ol1 total of p38, p39, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 30 ma v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v v ih3 p70 to p77 0.7av ref0 av ref0 v input voltage, high v ih4 x1, x2, xt1, xt2 v dd ? 0.5 v dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v v il3 p70 to p77 av ss 0.3av ref0 v input voltage, low v il4 x1, x2, xt1, xt2 v ss 0.4 v notes 1. p00, p01, p30, p41, p98, pcm0 to pcm3, pcs0 , pcs1, pct0, pct1 , pct4, pct6, pd l0 to pdl15 and their alternate-function pins. 2. reset, p02 to p06, p31 to p35, p3 8, p39, p40, p42, p50 to p55, p 90, p91, p96, p9 7, p99, p913 to p915 and their alternate-function pins. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 702 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (2/5) parameter symbol conditions min. typ. max. unit note 1 i oh = ? 2.0 ma, ev dd = 4.0 to 5.5 v ev dd ? 1.0 ev dd v output voltage, high v oh1 note 2 i oh = ? 0.1 ma, ev dd = 2.7 to 5.5 v ev dd ? 0.5 ev dd v v ol1 note 3 i ol = 2.0 ma note 4 0 0.8 v i ol = 15 ma, ev dd = 4.0 to 5.5 v 0 2.0 v i ol = 8 ma, ev dd = 3.0 to 5.5 v 0 1.0 v output voltage, low v ol2 p38, p39 i ol = 5 ma, ev dd = 2.7 to 5.5 v 0 1.0 v input leakage current, high i lih v in = v dd 3.0 a input leakage current, low i lil v in = 0 v ? 3.0 a output leakage current, high i loh v o = v dd 3.0 a output leakage current, low i lol v o = 0 v ? 3.0 a pull-up resistor r l v in = 0 v 10 30 100 k ? notes 1. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i oh = ? 30 ma, total of p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 and their alternate-function pins: i oh = ? 30 ma. 2. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i oh = ? 15 ma, total of p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 and their alternate-function pins: i oh = ? 15 ma. 3. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i ol = 30 ma, total of p38, p39, p50 to p55, p90, p91, p 96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 and their alternate-function pins: i ol = 30 ma. 4. refer to i ol1 for i ol of p38 and p39. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 703 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (3/5) parameter symbol conditions min. typ. max. unit f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 55 75 ma i dd1 normal operation mode all peripheral functions operating f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 29 43 ma i dd2 halt mode all peripheral functions operating f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma f xx = 5 mhz (when pll mode off) regc = v dd = 5 v 10% 2.1 3.3 ma i dd3 idle mode watch timer operating, ring oscillation stopped f x = 8 mhz (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma i dd4 subclock operation mode (f xt = 32.768 khz) main oscillation stopped, ring oscillation stopped 250 420 a i dd5 sub-idle mode (f xt = 32.768 khz) main oscillation stopped, ring oscillation stopped 20 75 a sub-oscillation operating, ring oscillation operating 34 103 a sub-oscillation stopped (xt1 = v ss ), ring oscillation operating 17.5 63.5 a i dd6 stop mode sub-oscillation stopped (xt1 = v ss ), ring oscillation stopped 3.5 35.5 a i dd7 note 2 ring clock operation mode (f xx = 240 khz) main oscillation stopped, sub-oscillation stopped 4 11 ma i dd8 note 2 ring halt mode (f xx = 240 khz) main oscillation stopped, sub-oscillation stopped t.b.d. t.b.d. ma f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 65 90 ma supply current note 1 ( pd70f3308, 70f3308y) i dd9 flash memory erase/write f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma notes 1. total current of v dd and ev dd (all ports stopped). av ref0 is not included. 2. the supply current of the main clo ck oscillator is not included since t he main clock oscillator is stopped because of an abnormality. remark f xx : main clock frequency f x : main clock oscillation frequency f xt : subclock frequency chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 704 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (4/5) parameter symbol conditions min. typ. max. unit f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 51 70 ma i dd1 normal operation mode all peripheral functions operating f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 25 38 ma i dd2 halt mode all peripheral functions operating f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma f xx = 5 mhz (when pll mode off) regc = v dd = 5 v 10% 1.8 2.9 ma i dd3 idle mode watch timer operating, ring oscillation stopped f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma i dd4 subclock operation mode (f xt = 32.768 khz) main oscillation stopped, ring oscillation stopped 240 400 a i dd5 sub-idle mode (f xt = 32.768 khz) main oscillation stopped, ring oscillation stopped 20 75 a sub-oscillation operating, ring oscillation operating 34 103 a sub-oscillation stopped (xt1 = v ss ), ring oscillation operating 17.5 63.5 a i dd6 stop mode sub-oscillation stopped (xt1 = v ss ), ring oscillation stopped 3.5 35.5 a i dd7 note 2 ring clock operation mode (f xx = 240 khz) main oscillation stopped, sub-oscillation stopped 3.5 10.5 ma i dd8 note 2 ring halt mode (f xx = 240 khz) main oscillation stopped, sub-oscillation stopped t.b.d. t.b.d. ma f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 61 85 ma supply current note 1 ( pd70f3306, 70f3306y) i dd9 flash memory erase/write f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma notes 1. total current of v dd and ev dd (all ports stopped). av ref0 is not included. 2. the supply current of the main clo ck oscillator is not included since t he main clock oscillator is stopped because of an abnormality. remark f xx : main clock frequency f x : main clock oscillation frequency f xt : subclock frequency chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 705 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (5/5) parameter symbol conditions min. typ. max. unit f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 42 60 ma i dd1 normal operation mode all peripheral functions operating f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma f xx = 20 mhz (f x = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 29 40 ma i dd2 halt mode all peripheral functions operating f xx = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma f x = 5 mhz (when pll mode off) regc = v dd = 5 v 10% 1.7 2.7 ma i dd3 idle mode watch timer operating, ring oscillation stopped f x = t.b.d. (in clock-through mode) regc = v dd = 3 v 10% t.b.d. t.b.d. ma i dd4 subclock operation mode (f xt = 32.768 khz) main oscillation stopped, ring oscillation stopped 100 220 a i dd5 sub-idle mode (f xt = 32.768 khz) main oscillation stopped, ring oscillation stopped 20 75 a sub-oscillation operating, ring oscillation operating 34 103 a sub-oscillation stopped (xt1 = v ss ), ring oscillation operating 17.5 63.5 a i dd6 stop mode sub-oscillation stopped (xt1 = v ss ), ring oscillation stopped 3.5 35.5 a i dd7 note 2 ring clock operation mode (f xx = 240 khz) main oscillation stopped, sub-oscillation stopped 3 9.5 ma supply current note 1 ( pd703308, 703308y) i dd8 note 2 ring halt mode (f xx = 240 khz) main oscillation stopped, sub-oscillation stopped t.b.d. t.b.d. a notes 1. total current of v dd and ev dd (all ports stopped). av ref0 is not included. 2. the supply current of the main clo ck oscillator is not included since t he main clock oscillator is stopped because of an abnormality. remark f xx : main clock frequency f x : main clock oscillation frequency f xt : subclock frequency chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 706 data retention characteristics stop mode (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 2.0 5.5 v stop release signal input time t drel 0 s caution shifting to stop mode and restoring from stop mode mu st be performed within the rated operating range. t drel stop release signal input stop mode setting v dddr v dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 707 ac characteristics ac test input measurement points ac test output measurement points load conditions v oh v ol v oh v ol measurement points ev dd ev ss dut (device under measurement) c l = 50 pf caution if the load capaci tance exceeds 50 pf due to the circ uit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. v dd , av ref0 , ev dd v ss , av ss , ev ss v ih v il v ih v il measurement points chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 708 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <1> 50 ns 30.6 s v dd = 4.0 to 5.5 v t cyk /2 ? 17 ns high-level width t wkh <2> v dd = 2.7 to 5.5 v t cyk /2 ? 26 ns v dd = 4.0 to 5.5 v t cyk /2 ? 17 ns low-level width t wkl <3> v dd = 2.7 to 5.5 v t cyk /2 ? 26 ns v dd = 4.0 to 5.5 v 17 ns rise time t kr <4> v dd = 2.7 to 5.5 v 26 ns v dd = 4.0 to 5.5 v 17 ns fall time t kf <5> v dd = 2.7 to 5.5 v 26 ns clock timing clkout (output) <1> <2> <3> <4> <5> chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 709 bus timing (1) read/write cycle (a) read/write cycle (clkout asynchronous) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <6> (0.5 + t asw )t ? 23 ns address hold time (from astb ) t hsta <7> (0.5 + t asw )t ? 15 ns delay time from rd to address float t frda <8> 16 ns data input setup time from address t said <9> (2 + n + t asw + t ahw )t ? 40 ns data input setup time from rd t srid <10> (1 + n + t asw + t ahw )t ? 25 ns delay time from astb to rd, wrm t dstrdwr <11> (0.5 + t ahw )t ? 20 ns data input hold time (from rd ) t hrdid <12> 0 ns address output time from rd t drda <13> (1 + i)t ? 16 ns delay time from rd, wrm to astb t drdwrst <14> 0.5t ? 10 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 10 ns rd, wrm low-level width t wrdwrl <16> (1 + n)t ? 10 ns astb high-level width t wsth <17> (1 + t asw )t ? 25 ns data output time from wrm t dwrod <18> 20 ns data output setup time (to wrm ) t sodwr <19> (1 + n)t ? 25 ns data output hold time (from wrm ) t hwrod <20> t ? 15 ns t sawt1 <21> n 1 (1.5 + t asw + t ahw )t ? 45 ns wait setup time (to address) t sawt2 <22> (1.5 + n + t asw + t ahw )t ? 45 ns t hawt1 <23> n 1 (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> n 1 (1 + t ahw )t ? 32 ns wait setup time (to astb ) t sstwt2 <26> (1 + n + t ahw )t ? 32 ns t hstwt1 <27> n 1 (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> (1 + n + t ahw )t ns remarks 1. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 710 (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <6> (0.5 + t asw )t ? 42 ns address hold time (from astb ) t hsta <7> (0.5 + t asw )t ? 30 ns delay time from rd to address float t frda <8> 32 ns data input setup time from address t said <9> (2 + n + t asw + t ahw )t ? 72 ns data input setup time from rd t srid <10> (1 + n + t asw + t ahw )t ? 40 ns delay time from astb to rd, wrm t dstrdwr <11> (0.5 + t ahw )t ? 35 ns data input hold time (from rd ) t hrdid <12> 0 ns address output time from rd t drda <13> (1 + i)t ? 32 ns delay time from rd, wrm to astb t drdwrst <14> 0.5t ? 20 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 20 ns rd, wrm low-level width t wrdwrl <16> (1 + n)t ? 20 ns astb high-level width t wsth <17> (1 + t asw )t ? 50 ns data output time from wrm t dwrod <18> 35 ns data output setup time (to wrm ) t sodwr <19> (1 + n)t ? 40 ns data output hold time (from wrm ) t hwrod <20> t ? 30 ns t sawt1 <21> n 1 (1.5 + t asw + t ahw )t ? 80 ns wait setup time (to address) t sawt2 <22> (1.5 + n + t asw + t ahw )t ? 80 ns t hawt1 <23> n 1 (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> n 1 (1 + t ahw )t ? 60 ns wait setup time (to astb ) t sstwt2 <26> (1 + n + t ahw )t ? 60 ns t hstwt1 <27> n 1 (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> (1 + n + t ahw )t ns caution set the following in accordan ce with the usage conditions of the cpu operating clock frequency (k = 0, 1). ? 70 ns < 1/ f cpu < 84 ns set an address setup wait (awc.aswk bit = 1). ? 62.5 ns < 1/ f cpu < 70 ns set an address setup wait (aswk bit = 1) and address hold wait (awc.ahwk bit = 1). remarks 1. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 711 read cycle (clkout asynchronous) clkout (output) cs0, cs1 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <6> <7> <17> <9> <12> <13> <10> <11> <25> <27> <26> <28> <21> <23> <22> <24> <16> <8> <14> <15> remark wr0 and wr1 are high level. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 712 write cycle (clkout asynchronous) clkout (output) ad0 to ad15 (i/o) astb (output) wr0 (output), wr1 (output) wait (input) t1 t2 tw t3 data address <25> <27> <26> <28> <21> <23> <22> <24> <6> <17> <7> <14> <20> <19> <16> <11> <18> cs0, cs1 (output) remark wr0 and wr1 are high level. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 713 (b) read/write cycle (clkout synchronous) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit delay time from clkout to address t dka <29> 0 19 ns delay time from clkout to address float t fka <30> 0 14 ns delay time from clkout to astb t dkst <31> 0 23 ns delay time from clkout to rd, wrm t dkrdwr <32> ? 22 0 ns data input setup time (to clkout ) t sidk <33> 15 ns data input hold time (from clkout ) t hkid <34> 0 ns data output delay time from clkout t dkod <35> 19 ns wait setup time (to clkout ) t swtk <36> 15 ns wait hold time (from clkout ) t hkwt <37> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit delay time from clkout to address t dka <29> 0 19 ns delay time from clkout to address float t fka <30> 0 18 ns delay time from clkout to astb t dkst <31> 0 55 ns delay time from clkout to rd, wrm t dkrdwr <32> ? 22 0 ns data input setup time (to clkout ) t sidk <33> 30 ns data input hold time (from clkout ) t hkid <34> 0 ns data output delay time from clkout t dkod <35> 19 ns wait setup time (to clkout ) t swtk <36> 25 ns wait hold time (from clkout ) t hkwt <37> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 714 read cycle (clkout synchronous) clkout (output) cs0, cs1 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <29> <31> <32> <30> <31> <32> <36> <36> <37> <37> <33> <34> remark wr0 and wr1 are high level. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 715 write cycle (clkout synchronous) clkout (output) ad0 to ad15 (i/o) astb (output) wr0 (output), wr1 (output) wait (input) t1 t2 tw t3 data address <29> <31> <32> <32> <37> <37> <36> <36> <31> <35> cs0, cs1 (output) remark rd is high level. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 716 (2) bus hold (a) clkout asynchronous (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit hldrq high-level width t whqh <78> t + 10 ns hldak low-level width t whal <79> t ? 15 ns delay time from hldak to bus output t dhac <80> ? 40 ns delay time from hldrq to hldak t dhqha1 <81> (2n + 7.5)t + 40 ns delay time from hldrq to hldak t dhqha2 <82> 0.5t 1.5t + 40 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit hldrq high-level width t whqh <78> t + 10 ns hldak low-level width t whal <79> t ? 15 ns delay time from hldak to bus output t dhac <80> ? 80 ns delay time from hldrq to hldak t dhqha1 <81> (2n + 7.5)t + 70 ns delay time from hldrq to hldak t dhqha2 <82> 0.5t 1.5t + 70 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 717 bus hold (clkout asynchronous) clkout (output) hldrq (input) hldak (output) ad0 to ad15 (i/o) th th th ti ti hi-z cs0, cs1 (output) hi-z astb (output) rd (output), wr0 (output), wr1 (output) hi-z hi-z <78> <82> <79> <80> <81> chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 718 (b) clkout synchronous (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <83> 15 ns hldrq hold time (from clkout ) t hkhq <84> 0 ns delay time from clkout to bus float t dkf <85> 20 ns delay time from clkout to hldak t dkha <86> 20 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <83> 25 ns hldrq hold time (from clkout ) t hkhq <84> 0 ns delay time from clkout to bus float t dkf <85> 40 ns delay time from clkout to hldak t dkha <86> 40 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 719 bus hold (clkout synchronous) clkout (output) hldrq (input) hldak (output) ad0 to ad15 (i/o) th th th t2 t3 ti ti hi-z cs0, cs1 (output) hi-z astb (output) rd (output), wr0 (output), wr1 (output) hi-z hi-z <83> <83> <86> <86> <84> <85> chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 720 basic operation (1) reset/external interrupt timing ( t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf ) parameter symbol conditions min. max. unit when digital noise elimination not selected 2 s t wrsl1 <87> reset in power-on status when digital noise elimination selected nr t rsmp + 2 s reset low-level width note t wrsl2 <88> power-on reset 3 ms nmi high-level width t wnih <89> analog noise elimination 1 s nmi low-level width t wnil <90> analog noise elimination 1 s n = 0 to 7 (analog noise elimination) 600 ns intpn high-level width t with <91> n = 3 (when digital noise elimination selected) ni t ismp + 200 ns n = 0 to 7 (analog noise elimination) 600 ns intpn low-level width t witl <92> n = 3 (when digital noise elimination selected) ni t ismp + 200 ns note the reset low-level width is when the reset pin input is valid (when pocres is invalid). remarks 1. nr: number of samplings t rsmp : digital noise elimination sa mpling clock cycle of reset pin ni: number of samplings t ismp : digital noise elimination sa mpling clock cycle of intp3 pin 2. the above specification shows the pulse width that is accurately detected as a valid edge. if a pulse narrower than the above specification is input, theref ore, it may also be detected as a valid edge. reset/interrupt <88> <87> v dd reset (input) nmi (input) intpn (input) <89> <90> <91> <92> remark n = 0 to 7 chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 721 timer timing ( t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf ) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 2t smp0 + 100 note 1 ns ti0n high-level width t ti0h <93> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 2t smp0 + 200 note 1 ns regc = v dd = 4.0 to 5.5 v 2t smp0 + 100 note 1 ns ti0n low-level width t ti0l <94> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 2t smp0 + 200 note 1 ns regc = v dd = 4.0 to 5.5 v 50 ns ti5m high-level width t ti5h <95> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns regc = v dd = 4.0 to 5.5 v 50 ns ti5m low-level width t ti5l <96> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns regc = v dd = 4.0 to 5.5 v np t smpp + 100 note 2 ns tip0m high-level width t tiph <97> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v np t smpp + 200 note 2 ns regc = v dd = 4.0 to 5.5 v np t smpp + 100 note 2 ns tip0m low-level width t tipl <98> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v np t smpp + 200 note 2 ns notes 1. t smp0 : timer 0 count clock cycle however, t smp0 = 4/f xx when ti0n is used as an external clock. 2. t smpp : digital noise elimination sa mpling clock cycle of tip0m pin if tip00 is used as an external event count input or an external trigger input, however, t smpp = 0 (digital noise is not eliminated). remarks 1. n = 00, 01, 10, 11 m = 0, 1 2. the above specification shows the pul se width that is accurately detected as a valid edge. if a pulse narrower than the above specification is input, theref ore, it may also be detected as a valid edge. timer input timing ti0n (input) ti5m (input) tip0m (input) <93>/<95>/<97> <94>/<96>/<98> remark n = 00, 01, 10, 11 m = 0, 1 chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 722 uart timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate 312.5 kbps regc = v dd = 4.0 to 5.5 v 12 mhz asck0 frequency regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 6 mhz chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 723 csi0 timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 200 ns sck0n cycle time t kcy1 <99> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 400 ns sck0n high-/low-level width t kh1 , t kl1 <100> t kcy1 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n setup time (to sck0n) t sik1 <101> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 50 ns regc = v dd = 5 v 10% 30 ns si0n hold time (from sck0n) t ksi1 <102> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 50 ns regc = v dd = 4.0 to 5.5 v 30 ns delay time from sck0n to so0n output t kso1 <103> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns remark n = 0, 1 (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 200 ns sck0n cycle time t kcy2 <99> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 400 ns regc = v dd = 4.0 to 5.5 v 45 ns sck0n high-/low-level width t kh2 , t kl2 <100> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 90 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n setup time (to sck0n) t sik2 <101> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n hold time (from sck0n) t ksi2 <102> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 50 ns delay time from sck0n to so0n output t kso2 <103> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns remark n = 0, 1 chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 724 csi0 timing so0n (output) input data output data si0n (input) sck0n (i/o) <99> <100> <100> <101> <102> <103> hi-z hi-z remarks 1. when transmit/receive type 1 (csicn.ckpn, csicn.dapn bits = 00) 2. n = 0, 1 chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 725 csia timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 500 ns scka0 cycle time t kcy3 <104> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 1000 ns scka0 high-/low-level width t kh3 , t kl3 <105> t kcy3 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 30 ns sia0 setup time (to scka0 ) t sik3 <106> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns sia0 hold time (from scka0 ) t ksi3 <107> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns delay time from scka0 to soa0 output t kso3 <108> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 840 ns scka0 cycle time t kcy4 <104> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 1700 ns scka0 high-/low-level width t kh4 , t kl4 <105> t kcy4 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 50 ns sia0 setup time (to scka0 ) t sik4 <106> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns regc = v dd = 4.0 to 5.5 v t cy 2 + 15 note ns sia0 hold time (from scka0 ) t ksi4 <107> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v t cy 2 + 30 note ns regc = v dd = 4.0 to 5.5 v t cy 2 + 30 note ns delay time from scka0 to soa0 output t kso4 <108> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v t cy 2 + 60 note ns note t cy : internal clock output cycle f xx (csis0.cksa01, csis0.cksa00 bits = 00), f xx /2 (cksa01, cksa00 bits = 01) f xx /2 2 (cksa01, cksa00 bits = 10), f xx /2 3 (cksa01, cksa00 bits = 11) chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 726 soa0 (output) input data output data sia0 (input) scka0 (i/o) <104> <105> <105> <106> <107> <108> hi-z hi-z chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 727 i 2 c bus mode ( pd703308y, 70f3306y, 70f3308y only) (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) normal mode high-speed mode parameter symbol min. max. min. max. unit scl0 clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <109> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <110> 4.0 ? 0.6 ? s scl0 clock low-level width t low <111> 4.7 ? 1.3 ? s scl0 clock high-level width t high <112> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <113> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <114> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <115> 250 ? 100 note 4 ? ns sda0 and scl0 signal rise time t r <116> ? 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f <117> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <118> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <119> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda0 signal (at v ihmin. of scl0 signal) in order to occupy the undef ined area at the falling edge of scl0. 3. if the system does not extend the scl0 signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high- speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0 signal?s low state hold time: t su : dat 250 ns ? if the system extends the scl0 signal?s low state hold time: transmit the following data bit to the sda0 line prior to the scl0 line release (t rmax. + t su:dat = 1000 + 250 = 1250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 728 i 2 c bus mode ( chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 729 a/d converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 av ref0 5.5 v 0.2 0.4 %fsr overall error note 1 ainl 2.7 av ref0 4.0 v 0.3 0.6 %fsr high-speed mode 3.0 100 s 4.5 av ref0 5.5 v normal mode 14.0 100 s high-speed mode 4.8 100 s 4.0 av ref0 4.5 v normal mode 14.0 100 s high-speed mode 6.0 100 s 2.85 av ref0 4.0 v normal mode 17.0 100 s high-speed mode 14.0 100 s conversion time t conv 2.7 av ref0 2.85 v normal mode 17.0 100 s 4.0 av ref0 5.5 v 0.4 %fsr zero-scale error note 1 e zs 2.7 av ref0 4.0 v 0.6 %fsr 4.0 av ref0 5.5 v 0.4 %fsr full-scale error note 1 e fs 2.7 av ref0 4.0 v 0.6 %fsr 4.0 av ref0 5.5 v 2.5 lsb non-linearity error note 2 ile 2.7 av ref0 4.0 v 4.5 lsb 4.0 av ref0 5.5 v 1.5 lsb differential linearity error note 2 dle 2.7 av ref0 4.0 v 2.0 lsb analog input voltage v ian 0 av ref0 v when using a/d converter 1.3 2.5 ma av ref0 current ia ref0 when not using a/d converter 1.0 t.b.d. a notes 1. excluding quantization error ( 0.05 %fsr). 2. excluding quantization error ( 0.5 lsb). remark lsb: least significant bit fsr: full scale range chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 730 power-on-clear circuit characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit detection voltage v poc 2.5 2.6 2.7 v power supply rise time t pth <120> v dd = 0 2.5 v 3 s response time 1 note 1 t pthd <121> after voltage reaches detection voltage (max.) on power application 3.0 ms response time 2 note 2 t pd <122> when power supply drops 1.0 ms minimum pulse width t pw <123> 0.2 ms notes 1. time from when the detection voltage (v poc ) is detected until the reset signal (pocres) is released 2. time from when the detection voltage (v poc ) is detected until the rese t signal (pocres) is generated power-on-clear circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) <123> <122> <120> <121> chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 731 low-voltage detector characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit 4.1 4.3 4.5 v 3.9 4.1 4.3 v 3.7 3.9 4.1 v 3.5 3.7 3.9 v 3.3 3.5 3.7 v 3.15 3.3 3.45 v detection voltage v lvi 2.95 3.1 3.25 v response time note 1 t ld <124> 0.2 2.0 ms minimum pulse width t lw <125> 0.2 ms operation stabilization wait time note 2 t wait1 <126> 0.1 0.2 ms notes 1. time from when the detection voltage (v lvi ) is detected until an interrupt r equest signal (intlvi) or reset signal (lvires) is generated 2. time from when the lvim.lvion bit = 1 until operation is stabilized low-voltage detector timing supply voltage (v dd ) time detection voltage (min.) operating voltage (min.) detection voltage (typ.) detection voltage (max.) <125> <124> <126> chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 732 flash memory programming characteristics (t a = ? 10 to +65 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (1) basic characteristics parameter symbol conditions min. typ. max. unit regc = v dd = 4.5 to 5.5 v 2 20 mhz regc = v dd = 4.0 to 5.5 v 2 16 mhz regc = capacity, v dd = 4.0 to 5.5 v 2 8 note 1 mhz programming operation frequency f cpu regc = v dd = 2.7 to 5.5 v 2 8 note 1 mhz supply voltage v dd 2.7 5.5 v overall erase time t era t.b.d. s write time t whb t.b.d. s number of rewrites c erwr note 2 100 times notes 1. these values may change after evaluation. 2. when writing initially to shipped products, it is also counted as one rewrite for ?write only?. example (p: write, e: erase) shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit setup time from v dd to flmd0 t dp <127> t.b.d. s release time from flmd0 to reset t pr <128> t.b.d. ms flmd0 pulse input start time from reset (after securing oscillation stabilization time) t rp <129> t.b.d. ms flmd0 pulse high-/low-level width t pw <130> t.b.d. t.b.d. s flmd0 pulse input end time from reset (after securing oscillation stabilization time) t rpe <131> t.b.d. ms 1st low data input time from reset (after securing oscillation stabilization time) t r1 <132> when uart communication is selected t.b.d. s time from 1st low data input to 2nd low data input t 12 <133> when uart communication is selected t.b.d. s time from 2nd low data input to reset command input t 2c <134> when uart communication is selected t.b.d. s low data input width t l1 /t l2 <135> when uart communication is selected 9600 bps time from reset (after securing oscillation stabilization time) to reset command input t rc <136> when csi or csi-hs communication is selected t.b.d. s chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 733 serial write operation timing (uart) v dd txd0 flmd1 0 v reset (input) flmd0 <128> rxd0 <133> <135> <132> <135> <134> <127> reset command remark the flmd0 pulse does not have to be input for uart0 communication. chapter 30 electrical specifications (target) preliminary user?s manual u16895ej1v0ud 734 serial write operation timing (csi or csi-hs) v dd sck00 flmd1 0 v reset (input) flmd0 <128> <129> <127> <130> <130> <131> <136> so00 si00 reset command preliminary user?s manual u16895ej1v0ud 735 chapter 31 package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h chapter 31 package drawings preliminary user?s manual u16895ej1v0ud 736 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f 1.25 14.0 0.2 b 12.0 0.2 m n 0.08 0.145 0.05 p q 0.1 0.05 1.0 j 0.5 (t.p.) k l 0.5 1.0 0.2 i 0.08 s 1.1 0.1 r 3 + 4 ? 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u 0.6 0.15 preliminary user?s manual u16895ej1v0ud 737 appendix a development tools the following development tool s are available for the dev elopment of systems that em ploy the v850es/kf1+. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, products supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98, 2000 ? windows me ? windows xp ? windows nt tm ver. 4.0 appendix a development tools preliminary user?s manual u16895ej1v0ud 738 figure a-1. development tool configuration language processing software ? c compiler package ? device file debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter note 2 in-circuit emulator (qb-v850eskx1h) note 3 conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory ? project manager (windows only) note 1 software package control software embedded software ? real-time os ? network library ? file system power supply unit flash memory write environment notes 1. the project manager pm plus is included in the c compiler package. the pm plus is only used for windows. 2. qb-v850eskx1h supports usb only. 3. qb-v850eskx1h is supplied with id850qb, a devi ce file, and power supply unit. any other products are sold separately. appendix a development tools preliminary user?s manual u16895ej1v0ud 739 a.1 software package development tools (software) common to the v850 series are combined in this package. sp850 v850 series software package part number: s sp850 remark in the part number differs depending on the host machine and os used. s sp850 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler is st arted from project manager pm plus. ca850 c compiler package part number: s ca703000 df703308 device file this file contains information peculiar to the device. this device file should be used in combinat ion with a tool (ca850, sm850, and id850qb). the corresponding os and host machine di ffer depending on the tool to be used. remark in the part number differs depending on the host machine and os used. s ca703000 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom a.3 control software pm plus project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the pm plus. appendix a development tools preliminary user?s manual u16895ej1v0ud 740 a.4 debugging tools (hardware) a.4.1 when using in-circuit emulator qb-v850eskx1h qb-v850eskx1h notes 1, 2 in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using a v850es/kf1+ pr oduct. it corresponds to the integrated debugger id850qb. this emulator should be used in combination with a power supply unit and emulation probe. use usb to connect this emulator to the host machine. emulation probe for gc package note 2 (part number pending) this probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic qfp (gc-8bt type). emulation probe for gk package note 2 (part number pending) this probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic tqfp (gk-9eu type). notes 1. qb-v850eskx1h is supplied with a power supply unit. it is also supplied with integrated debugger id850qb and a device file as control software. 2. under development a.5 debugging tools (software) this is a system simulator for the v850 series. the sm plus is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm plus allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. it should be used in combination with the device file (sold separately). sm plus note system simulator part number: s sm703100 id850qb integrated debugger (supporting in-circuit emulator qb-v850eskx1h) this debugger supports the in-circuit emulat ors for the v850 series. the id850qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memo ry display with the trace result. it should be used in combination with the device file (sold separately). note under development remark in the part number differs depending on the host machine and os used. s sm703100 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom appendix a development tools preliminary user?s manual u16895ej1v0ud 741 a.6 embedded software the rx850 and rx850 pro are real-time oss conforming to itron 3.0 specifications. a tool (configurator) for generating multiple information tables is supplied. rx850 pro has more functions than rx850. rx850, rx850 pro real-time os part number: s rx703000- ???? (rx850) s rx703100- ???? (rx850 pro) v850mini-net note (provisional name) (network library) this is a network library conforming to rfc. it is a lightweight tcp/ip of compact design, requiring only a small memory. in addition to the tcp/ip standard set, an http server, smtp client , and pop client are also supported. rx-fs850 (file system) this is a fat file system function. it is a file system that supports the cd-rom file system function. this file system is used with the real-time os rx850 pro. note under development caution to purchase the rx850 or rx850 pro, first fill in the purchase applicati on form and sign the user agreement. remark and ???? in the part number differ depending on the host machine and os used. s rx703000- ???? s rx703100- ???? ???? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k 0.1 million units 001m 1 million units 010m mass-production object 10 million units s01 source program object source program for mass production host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation solaris (rel. 2.5.1) cd-rom a.7 flash memory writing tools flashpro iv (part number: pg-fp4) flash programmer flash programmer dedicated to microcont rollers with on-chip flash memory. fa-80gc-8bt-a flash memory writing adapter flash memory writing adapter used connected to the flashpro iv. ? fa-80gc-8bt-a: for 80-pin plastic qfp (gc-8bt type) fa-80gk-9eu-a flash memory writing adapter flash memory writing adapter used connected to the flashpro iv. ? fa-80gk-9eu-a: for 80-pin plastic tqfp (gk-9eu type) remark fa-80gc-8bt-a and fa-80gk-9eu-a are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. preliminary user?s manual u16895ej1v0ud 742 appendix b instruction set list b.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the re mainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the condition codes sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list appendix b instruction set list preliminary user?s manual u16895ej1v0ud 743 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency). appendix b instruction set list preliminary user?s manual u16895ej1v0ud 744 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z 0 0 1 0 z = 1 zero nz 1 0 1 0 z = 0 not zero nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) s/n 0 1 0 0 s = 1 negative ns/p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed appendix b instruction set list preliminary user?s manual u16895ej1v0ud 745 b.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 r r r r r 0 1 0 010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 4 4 4 bit#3,disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 r r r r r 1 1 1 111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 r r r r r 0 1 0 011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r appendix b instruction set list preliminary user?s manual u16895ej1v0ud 746 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11 appendix b instruction set list preliminary user?s manual u16895ej1v0ud 747 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-exend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-exend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 r r r r r 0 1 0 000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 r r r r r 0 1 0 111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3 appendix b instruction set list preliminary user?s manual u16895ej1v0ud 748 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp+4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5)) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16)) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 appendix b instruction set list preliminary user?s manual u16895ej1v0ud 749 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 appendix b instruction set list preliminary user?s manual u16895ej1v0ud 750 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the total number of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states). appendix b instruction set list preliminary user?s manual u16895ej1v0ud 751 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. preliminary user?s manual u16895ej1v0ud 752 appendix c register index (1/7) symbol name unit page adcr a/d conversion result register adc 398 adcrh a/d conversion result register h adc 398 adic interrupt control register intc 592 adm a/d converter mode register adc 394 ads analog input channel specification register adc 397 adtc0 automatic data transfer address count register 0 csia 483 adti0 automatic data transfer interval specification register 0 csia 489 adtp0 automatic data transfer address point specification register 0 csia 487 asicl0 lin operation control register 0 uart 426 asif0 asynchronous serial interface tr ansmit status register 0 uart 424 asif1 asynchronous serial interface tr ansmit status register 1 uart 424 asim0 asynchronous serial interface mode register 0 uart 421 asim1 asynchronous serial interface mode register 1 uart 421 asis0 asynchronous serial interface status register 0 uart 423 asis1 asynchronous serial interface status register 1 uart 423 awc address wait control register bcu 162 bcc bus cycle control register bcu 163 brgc0 baud rate generator control register 0 uart 447 brgc1 baud rate generator control register 1 uart 447 brgca0 divisor selection register 0 csia 487 brgic interrupt control register intc 592 bsc bus size configuration register bcu 152 ccls cpu operation clock status register cg 178 cksr0 clock select register 0 uart 446 cksr1 clock select register 1 uart 446 clm clock monitor mode register clm 650 cmp00 8-bit timer h compare register 00 tmh 340 cmp01 8-bit timer h compare register 01 tmh 340 cmp10 8-bit timer h compare register 10 tmh 340 cmp11 8-bit timer h compare register 11 tmh 340 corad0 correction address register 0 romc 669 corad0h correction address register 0h romc 669 corad0l correction address register 0l romc 669 corad1 correction address register 1 romc 669 corad1h correction address register 1h romc 669 corad1l correction address register 1l romc 669 corad2 correction address register 2 romc 669 corad2h correction address register 2h romc 669 corad2l correction address register 2l romc 669 corad3 correction address register 3 romc 669 corad3h correction address register 3h romc 669 appendix c register index preliminary user?s manual u16895ej1v0ud 753 (2/7) symbol name unit page corad3l correction address register 3l romc 669 corcn correction control register romc 670 cr000 16-bit timer capture/compare register 000 tm0 272 cr001 16-bit timer capture/compare register 001 tm0 274 cr010 16-bit timer capture/compare register 010 tm0 272 cr011 16-bit timer capture/compare register 011 tm0 274 cr5 16-bit timer compare register 5 tm5 321 cr50 8-bit timer compare register 50 tm5 321 cr51 8-bit timer compare register 51 tm5 321 crc00 capture/compare control register 00 tm0 277 crc01 capture/compare control register 01 tm0 277 csi0ic0 interrupt control register intc 592 csi0ic1 interrupt control register intc 592 csia0b0 csia0 buffer ramn (n = 0 to f) csia 489 csia0b0h csia0 buffer ramnh (n = 0 to f) csia 489 csia0b0l csia0 buffer ramnl (n = 0 to f) csia 489 csiaic0 interrupt control register intc 592 csic0 clocked serial interface cl ock selection register 0 csi0 459 csic1 clocked serial interface cl ock selection register 1 csi0 459 csim00 clocked serial interfac e mode register 00 csi0 457 csim01 clocked serial interfac e mode register 01 csi0 457 csima0 serial operation mode specification register 0 csia 484 csis0 serial status register 0 csia 485 csit0 serial trigger register 0 csia 486 ctbp callt base pointer cpu 53 ctpc callt execution status saving register cpu 52 ctpsw callt execution status saving register cpu 52 dbpc exception/debug trap status saving register cpu 53 dbpsw exception/debug trap status saving register cpu 53 dwc0 data wait control register 0 bcu 160 ecr interrupt source register cpu 50 eipc interrupt status saving register cpu 49 eipsw interrupt status saving register cpu 49 fepc nmi status saving register cpu 50 fepsw nmi status saving register cpu 50 iic0 iic shift register 0 i 2 c 528 iicc0 iic control register 0 i 2 c 516 iiccl0 iic clock selection register 0 i 2 c 526 iicf0 iic flag register 0 i 2 c 524 iicic0 interrupt control register intc 592 iics0 iic status register 0 i 2 c 521 iicx0 iic function expansion register 0 i 2 c 527 imr0 interrupt mask register 0 intc 594 imr0h interrupt mask register 0h intc 594 appendix c register index preliminary user?s manual u16895ej1v0ud 754 (3/7) symbol name unit page imr0l interrupt mask register 0l intc 594 imr1 interrupt mask register 1 intc 594 imr1h interrupt mask register 1h intc 594 imr1l interrupt mask register 1l intc 594 imr3 interrupt mask register 3 intc 594 imr3l interrupt mask register 3l intc 594 intf0 external interrupt falling edge specification register 0 intc 601 intf3 external interrupt falling edge specification register 3 intc 602 intf9h external interrupt falling edge specification register 9h intc 603 intr0 external interrupt rising edge specification register 0 intc 601 intr3 external interrupt rising edge specification register 3 intc 602 intr9h external interrupt rising edge specification register 9h intc 603 ispr in-service priority register intc 595 kric interrupt control register intc 592 krm key return mode register kr 616 lviic interrupt control register intc 592 lvim low-voltage detection register lvi 660 lvis low-voltage detection level selection register lvi 661 nfc digital noise elimination control register intc 599 osts oscillation stabilization time selection register standby 622 p0 port 0 register port 88 p0nfc tip00 noise elimination control register tmp 267 p1nfc tip01 noise elimination control register tmp 267 p3 port 3 register port 91 p3h port 3 register h port 91 p3l port 3 register l port 91 p4 port 4 register port 96 p5 port 5 register port 98 p7 port 7 register port 101 p9 port 9 register port 103 p9h port 9 register h port 103 p9l port 9 register l port 103 pc program counter cpu 47 pcc processor clock control register cg 174 pcm port cm register port 108 pcs port cs register port 110 pct port ct register port 112 pdl port dl register port 115 pdlh port dl register h port 115 pdll port dl register l port 115 pf3h port 3 function register h port 93 pf4 port 4 function register port 97 pf5 port 5 function register port 99 pf9h port 9 function register h port 105 appendix c register index preliminary user?s manual u16895ej1v0ud 755 (4/7) symbol name unit page pfc3 port 3 function control register port 93 pfc5 port 5 function control register port 100 pfc9 port 9 function control register port 106 pfc9h port 9 function control register h port 106 pfc9l port 9 function control register l port 106 pfce3 port 3 function control expansion register port 93 pfm power fail comparison mode register adc 400 pft power fail comparison threshold register adc 400 pic0 interrupt control register intc 592 pic1 interrupt control register intc 592 pic2 interrupt control register intc 592 pic3 interrupt control register intc 592 pic4 interrupt control register intc 592 pic5 interrupt control register intc 592 pic6 interrupt control register intc 592 pic7 interrupt control register intc 592 pllctl pll control register cg 180, 389 pm0 port 0 mode register port 88 pm3 port 3 mode register port 91 pm3h port 3 mode register h port 91 pm3l port 3 mode register l port 91 pm4 port 4 mode register port 96 pm5 port 5 mode register port 98 pm9 port 9 mode register port 103 pm9h port 9 mode register h port 103 pm9l port 9 mode register l port 103 pmc0 port 0 mode control register port 89 pmc3 port 3 mode control register port 92 pmc3h port 3 mode control register h port 92 pmc3l port 3 mode control register l port 92 pmc4 port 4 mode control register port 96 pmc5 port 5 mode control register port 99 pmc9 port 9 mode control register port 104 pmc9h port 9 mode control register h port 104 pmc9l port 9 mode control register l port 104 pmccm port cm mode control register port 109 pmccs port cs mode control register port 111 pmcct port ct mode control register port 113 pmcdl port dl mode control register port 116 pmcdlh port dl mode control register h port 116 pmcdll port dl mode control register l port 116 pmcm port cm mode register port 108 pmcs port cs mode register port 110 appendix c register index preliminary user?s manual u16895ej1v0ud 756 (5/7) symbol name unit page pmct port ct mode register port 112 pmdl port dl mode register port 115 pmdlh port dl mode register h port 115 pmdll port dl mode register l port 115 prcmd command register cpu 76 prm00 prescaler mode register 00 tm0 280 prm01 prescaler mode register 01 tm0 280 prscm interval timer brg compare register cg 364 prsm interval timer brg mode register cg 363 psc power save control register standby 620 psmr power save mode register standby 621 psw program status word cpu 51 pu0 pull-up resistor option register 0 port 89 pu3 pull-up resistor option register 3 port 94 pu4 pull-up resistor option register 4 port 97 pu5 pull-up resistor option register 5 port 100 pu9 pull-up resistor option register 9 port 107 pu9h pull-up resistor option register 9h port 107 pu9l pull-up resistor option register 9l port 107 pucm pull-up resistor option register cm port 109 pucs pull-up resistor option register cs port 111 puct pull-up resistor option register ct port 113 pudl pull-up resistor option register dl port 116 pudll pull-up resistor option register dll port 116 pudlh pull-up resistor option register dlh port 116 rcm ring-osc mode register cg 178, 651 r0 to r31 general-purpose registers cpu 47 resf reset source flag register reset 637 rnzc reset noise elimination control register reset 640 rtbh0 real-time output buffer register h0 rtp 383 rtbl0 real-time output buffer register l0 rtp 383 rtpc0 real-time output port control register 0 rtp 385 rtpm0 real-time output port mode register 0 rtp 384 rxb0 receive buffer register 0 uart 425 rxb1 receive buffer register 1 uart 425 selcnt0 selector operation control register 0 uart 427 selcnt1 selector operation control register 1 tm0 281 sio00 serial i/o shift register 0 csi0 464 sio00l serial i/o shift register 0l csi0 464 sio01 serial i/o shift register 1 csi0 464 sio01l serial i/o shift register 1l csi0 464 sioa0 serial i/o shift register a0 csia 483 sirb0 clocked serial interface re ceive buffer register 0 csi0 460 appendix c register index preliminary user?s manual u16895ej1v0ud 757 (6/7) symbol name unit page sirb0l clocked serial interface re ceive buffer register 0l csi0 460 sirb1 clocked serial interface re ceive buffer register 1 csi0 460 sirb1l clocked serial interface re ceive buffer register 1l csi0 460 sirbe0 clocked serial interface read- only receive buffer register 0 csi0 461 sirbe0l clocked serial interface read- only receive buffer register 0l csi0 461 sirbe1 clocked serial interface read- only receive buffer register 1 csi0 461 sirbe1l clocked serial interface read- only receive buffer register 1l csi0 461 sotb0 clocked serial interface tr ansmit buffer register 0 csi0 462 sotb0l clocked serial interface tr ansmit buffer register 0l csi0 462 sotb1 clocked serial interface tr ansmit buffer register 1 csi0 462 sotb1l clocked serial interface tr ansmit buffer register 1l csi0 462 sotbf0 clocked serial interface init ial transmit buffer register 0 csi0 463 sotbf0l clocked serial interface init ial transmit buffer register 0l csi0 463 sotbf1 clocked serial interface init ial transmit buffer register 1 csi0 463 sotbf1l clocked serial interface init ial transmit buffer register 1l csi0 463 sreic0 interrupt control register intc 592 sreic1 interrupt control register intc 592 sric0 interrupt control register intc 592 sric1 interrupt control register intc 592 stic0 interrupt control register intc 592 stic1 interrupt control register intc 592 sva0 slave address register 0 i 2 c 528 sys system status register cpu 77 tcl50 timer clock selection register 50 tm5 322 tcl51 timer clock selection register 51 tm5 322 tm00 16-bit timer counter 00 tm0 272 tm01 16-bit timer counter 01 tm0 272 tm0ic00 interrupt control register intc 592 tm0ic01 interrupt control register intc 592 tm0ic10 interrupt control register intc 592 tm0ic11 interrupt control register intc 592 tm5 16-bit timer counter 5 tm5 335 tm50 8-bit timer counter 50 tm5 320 tm51 8-bit timer counter 51 tm5 320 tm5ic0 interrupt control register intc 592 tm5ic1 interrupt control register intc 592 tmc00 16-bit timer mode control register 00 tm0 275 tmc01 16-bit timer mode control register 01 tm0 275 tmc50 8-bit timer mode control register 50 tm5 323 tmc51 8-bit timer mode control register 51 tm5 323 tmcyc0 8-bit timer h carrier control register 0 tmh 344 tmcyc1 8-bit timer h carrier control register 1 tmh 344 tmhic0 interrupt control register intc 592 tmhic1 interrupt control register intc 592 appendix c register index preliminary user?s manual u16895ej1v0ud 758 (7/7) symbol name unit page tmhmd0 8-bit timer h mode register 0 tmh 341 tmhmd1 8-bit timer h mode register 1 tmh 341 toc00 16-bit timer output control register 00 tm0 278 toc01 16-bit timer output control register 01 tm0 278 tp0ccic0 interrupt control register intc 592 tp0ccic1 interrupt control register intc 592 tp0ccr0 tmp0 capture/compare register 0 tmp 191 tp0ccr1 tmp0 capture/compare register 1 tmp 193 tp0cnt tmp0 counter read buffer register tmp 195 tp0ctl0 tmp0 control register 0 tmp 185 tp0ctl1 tmp0 control register 1 tmp 186 tp0ioc0 tmp0 i/o control register 0 tmp 187 tp0ioc1 tmp0 i/o control register 1 tmp 188 tp0ioc2 tmp0 i/o control register 2 tmp 189 tp0opt0 tmp0 option register 0 tmp 190 tp0ovic interrupt control register intc 592 txb0 transmit buffer register 0 uart 425 txb1 transmit buffer register 1 uart 425 vswc system wait control register cpu 78 wdcs watchdog timer clock se lection register wdt 374 wdt1ic interrupt control register intc 592 wdte watchdog timer enable register wdt 380 wdtm1 watchdog timer mode register 1 wdt 375, 597 wdtm2 watchdog timer mode register 2 wdt 379 wtic interrupt control register intc 592 wtiic interrupt control register intc 592 wtm watch timer operation mode register wt 367 |
Price & Availability of UPD703308GC-XXX-8BT
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |